[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR

[Richard Spiegel (Code Review)]

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/28608 )

Change subject: amd/stoneyridge: Sync PSP base to MSR
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Patch Set 1:

(1 comment)

The idea that the TPM problem was due to a general protection fault seems to be the correct one.

https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c
File src/soc/amd/stoneyridge/cpu.c:

https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c@123
PS1, Line 123: 	setup_lapic();
I did a small modification based on your code, and tested. It worked through reboot and through S3 resume. I did not saw any GPF.

static void model_15_init(struct device *dev)
{
	check_mca();
	setup_lapic();

	/* Per AMD, sync an undocumented MSR with the PSP base address */
	msr_t psp_msr;
	uint32_t psp_bar; /* Note: NDA BKDG names this 32-bit register BAR3 */
	psp_bar = pci_read_config32(SOC_PSP_DEV, PCI_BASE_ADDRESS_4);
	psp_bar &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
	psp_msr = rdmsr(0xc00110a2);
	if (psp_msr.lo == 0) {
		psp_msr.hi = 0; //This line might not be needed.
		psp_msr.lo = psp_bar;
		wrmsr(0xc00110a2, psp_msr);
	}
}



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Gerrit-Change-Number: 28608
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall at amd.corp-partner.google.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Richard Spiegel <richard.spiegel at silverbackltd.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Fri, 14 Sep 2018 20:58:02 +0000
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