[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Sync PSP base to MSR

[Marshall Dawson (Code Review)]

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28608 )

Change subject: amd/stoneyridge: Sync PSP base to MSR
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Patch Set 1:

(1 comment)

It may be worth another try to ask AMD why they think the GPF occurs.

https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c
File src/soc/amd/stoneyridge/cpu.c:

https://review.coreboot.org/#/c/28608/1/src/soc/amd/stoneyridge/cpu.c@123
PS1, Line 123: 	setup_lapic();
> I did a small modification based on your code, and tested. […]
It'd be nice to comment properly what's really needed.  Did you check whether the value survived the S3 cycle?

Maybe there's a lock on the register?  Perhaps engaged when we call psp_notify_boot_done(), so I'd probably experiment with jamming the MSR at various times to see whether I can create a GPF.

Seems unlikely that it would be writable only a single time.



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Gerrit-Project: coreboot
Gerrit-Branch: master
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Gerrit-Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Gerrit-Change-Number: 28608
Gerrit-PatchSet: 1
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Garrett Kirkendall <garrett.kirkendall at amd.corp-partner.google.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
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Gerrit-Comment-Date: Tue, 18 Sep 2018 18:30:08 +0000
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