[coreboot-gerrit] Change in coreboot[master]: src/drivers/intel/fsp1_1: Configure UART after memory init
Frans Hendriks (Code Review)
gerrit at coreboot.org
Tue Sep 4 14:12:00 CEST 2018
Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/28464
Change subject: src/drivers/intel/fsp1_1: Configure UART after memory init
......................................................................
src/drivers/intel/fsp1_1: Configure UART after memory init
FSP code will default enable the onboard serial port.
When external serial port is used, this onboard port needs to be
disabled.
Add function mainboard_after_memory_init() function to perform
required actions to re-enabled output to external serial port.
BUG=N/A
TEST=LPC Post card on Intel Cherry Hill
Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Signed-off-by: Frans Hendriks <fhendriks at eltan.com>
---
M src/drivers/intel/fsp1_1/include/fsp/romstage.h
M src/drivers/intel/fsp1_1/raminit.c
2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28464/1
diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
index d79be70..1524fe2 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h
@@ -3,6 +3,7 @@
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015-2016 Intel Corporation
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -92,5 +93,6 @@
/* Update the SOC specific memory config param for mma. */
void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,
struct mma_config_param *mma_cfg);
+void mainboard_after_memory_init(void);
#endif /* _COMMON_ROMSTAGE_H_ */
diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index e5714ae..1af1ad0 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2014-2016 Intel Corporation
+ * Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -125,6 +126,7 @@
timestamp_add_now(TS_FSP_MEMORY_INIT_START);
post_code(POST_FSP_MEMORY_INIT);
status = fsp_memory_init(&fsp_memory_init_params);
+ mainboard_after_memory_init();
post_code(0x37);
timestamp_add_now(TS_FSP_MEMORY_INIT_END);
@@ -319,3 +321,10 @@
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
+
+/* Initialize the SoC after MemoryInit */
+__weak void mainboard_after_memory_init(
+ void)
+{
+ printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d
Gerrit-Change-Number: 28464
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
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