<p>Frans Hendriks has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28464">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/drivers/intel/fsp1_1: Configure UART after memory init<br><br>FSP code will default enable the onboard serial port.<br>When external serial port is used, this onboard port needs to be<br>disabled.<br>Add function mainboard_after_memory_init() function to perform<br>required actions to re-enabled output to external serial port.<br><br>BUG=N/A<br>TEST=LPC Post card on Intel Cherry Hill<br><br>Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d<br>Signed-off-by: Frans Hendriks <fhendriks@eltan.com><br>---<br>M src/drivers/intel/fsp1_1/include/fsp/romstage.h<br>M src/drivers/intel/fsp1_1/raminit.c<br>2 files changed, 11 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28464/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h</span><br><span>index d79be70..1524fe2 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h</span><br><span>+++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h</span><br><span>@@ -3,6 +3,7 @@</span><br><span>  *</span><br><span>  * Copyright (C) 2014 Google Inc.</span><br><span>  * Copyright (C) 2015-2016 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -92,5 +93,6 @@</span><br><span> /* Update the SOC specific memory config param for mma. */</span><br><span> void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg,</span><br><span>          struct mma_config_param *mma_cfg);</span><br><span style="color: hsl(120, 100%, 40%);">+void mainboard_after_memory_init(void);</span><br><span> </span><br><span> #endif /* _COMMON_ROMSTAGE_H_ */</span><br><span>diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c</span><br><span>index e5714ae..1af1ad0 100644</span><br><span>--- a/src/drivers/intel/fsp1_1/raminit.c</span><br><span>+++ b/src/drivers/intel/fsp1_1/raminit.c</span><br><span>@@ -2,6 +2,7 @@</span><br><span>  * This file is part of the coreboot project.</span><br><span>  *</span><br><span>  * Copyright (C) 2014-2016 Intel Corporation</span><br><span style="color: hsl(120, 100%, 40%);">+ * Copyright (C) 2018 Eltan B.V.</span><br><span>  *</span><br><span>  * This program is free software; you can redistribute it and/or modify</span><br><span>  * it under the terms of the GNU General Public License as published by</span><br><span>@@ -125,6 +126,7 @@</span><br><span>        timestamp_add_now(TS_FSP_MEMORY_INIT_START);</span><br><span>         post_code(POST_FSP_MEMORY_INIT);</span><br><span>     status = fsp_memory_init(&fsp_memory_init_params);</span><br><span style="color: hsl(120, 100%, 40%);">+        mainboard_after_memory_init();</span><br><span>       post_code(0x37);</span><br><span>     timestamp_add_now(TS_FSP_MEMORY_INIT_END);</span><br><span> </span><br><span>@@ -319,3 +321,10 @@</span><br><span> {</span><br><span>   printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Initialize the SoC after MemoryInit */</span><br><span style="color: hsl(120, 100%, 40%);">+__weak void mainboard_after_memory_init(</span><br><span style="color: hsl(120, 100%, 40%);">+ void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+      printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28464">change 28464</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28464"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d </div>
<div style="display:none"> Gerrit-Change-Number: 28464 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Frans Hendriks <fhendriks@eltan.com> </div>