[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell/gma: Support boards that have DDI E connected

[Tristan Corrick (Code Review)]

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29385


Change subject: nb/intel/haswell/gma: Support boards that have DDI E connected
......................................................................

nb/intel/haswell/gma: Support boards that have DDI E connected

On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.

Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.

[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
     Volume 2c: Command Reference: Registers (Haswell)
     https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family

Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan at corrick.kiwi>
---
M src/northbridge/intel/haswell/chip.h
M src/northbridge/intel/haswell/gma.c
2 files changed, 6 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29385/1

diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index 098bc33..fdabc3f 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -40,6 +40,8 @@
 	u32 gpu_cpu_backlight;	/* CPU Backlight PWM value */
 	u32 gpu_pch_backlight;	/* PCH Backlight PWM value */
 
+	bool gpu_ddi_e_connected;
+
 	struct i915_gpu_controller_info gfx;
 };
 
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index efc9fa3..f4cec68 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -368,7 +368,10 @@
 	   bit 4: DDI A supports 4 lanes and DDI E is not used
 	   bit 7: DDI buffer is idle
 	*/
-	gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED);
+	reg32 = DDI_BUF_IS_IDLE | DDI_INIT_DISPLAY_DETECTED;
+	if (!conf->gpu_ddi_e_connected)
+		reg32 |= DDI_A_4_LANES;
+	gtt_write(DDI_BUF_CTL_A, reg32);
 
 	/* Set FDI registers - is this required? */
 	gtt_write(_FDI_RXA_MISC, 0x00200090);

-- 
To view, visit https://review.coreboot.org/29385
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Gerrit-Change-Number: 29385
Gerrit-PatchSet: 1
Gerrit-Owner: Tristan Corrick <tristan at corrick.kiwi>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181031/5a538c9f/attachment-0001.html>