[coreboot-gerrit] Change in coreboot[master]: amd: [test] Fix IORR0 MTRR
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue Oct 30 07:08:45 CET 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29352
Change subject: amd: [test] Fix IORR0 MTRR
......................................................................
amd: [test] Fix IORR0 MTRR
Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/amd/agesa/family12/fixme.c
M src/cpu/amd/agesa/family14/fixme.c
M src/cpu/amd/agesa/family15tn/fixme.c
M src/cpu/amd/agesa/family16kb/fixme.c
M src/cpu/amd/mtrr/amd_mtrr.c
M src/cpu/amd/pi/00630F01/fixme.c
M src/cpu/amd/pi/00660F01/fixme.c
M src/cpu/amd/pi/00730F01/fixme.c
M src/include/cpu/amd/mtrr.h
M src/northbridge/amd/agesa/family15tn/northbridge.c
M src/northbridge/amd/agesa/family16kb/northbridge.c
M src/northbridge/amd/amdmct/mct/mctdqs_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
M src/northbridge/amd/pi/00630F01/northbridge.c
M src/northbridge/amd/pi/00660F01/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
16 files changed, 7 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/1
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
index 9df43e5..faaff23 100644
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -17,7 +17,6 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
#include "amdlib.h"
void amd_initcpuio(void)
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index a49cefb..4957b07 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -17,7 +17,6 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
#include "amdlib.h"
/* Define AMD Ontario APPU SSID/SVID */
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index a0ae193..0a02389 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -17,7 +17,6 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
#include "amdlib.h"
void amd_initcpuio(void)
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index 2d74c7b..d27355d 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -17,7 +17,6 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
#include "amdlib.h"
void amd_initcpuio(void)
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 8cb6658..3c581f0 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
@@ -138,7 +138,7 @@
* undefined side effects.
*/
msr.lo = msr.hi = 0;
- for (i = IORR_FIRST; i <= IORR_LAST; i++)
+ for (i = IORR0_BASE; i <= IORR1_MASK; i++)
wrmsr(i, msr);
/* Enable Variable Mtrrs
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index ae2a2df..5b3e0c8 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -18,7 +18,6 @@
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
-#include <AGESA.h>
#include <amdlib.h>
void amd_initcpuio(void)
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index e028b6f..95bee23 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -18,7 +18,6 @@
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
-#include <AGESA.h>
#include <amdlib.h>
void amd_initcpuio(void)
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 163066b..f415b36 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -18,7 +18,6 @@
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
-#include <AGESA.h>
#include <amdlib.h>
void amd_initcpuio(void)
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index 46d66f8..d139eca 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -1,20 +1,10 @@
#ifndef CPU_AMD_MTRR_H
#define CPU_AMD_MTRR_H
-/* FIXME
- * Replace
- * #define IORR_FIRST 0xC0010016
- * #define IORR_LAST 0xC0010019
- * with
- * #define IORR0_BASE 0xC0010016
- * #define IORR0_MASK 0xC0010017
- * #define IORR1_BASE 0xC0010018
- * #define IORR1_MASK 0xC0010019
- * those are also defined in vendorcode <AGESA.h> file.
- */
-
-#define IORR_FIRST 0xC0010016
-#define IORR_LAST 0xC0010019
+#define IORR0_BASE 0xC0010016
+#define IORR0_MASK 0xC0010017
+#define IORR1_BASE 0xC0010018
+#define IORR1_MASK 0xC0010019
#define MTRR_READ_MEM (1 << 4)
#define MTRR_WRITE_MEM (1 << 3)
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 7248eb7..fb2ca61 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -28,7 +28,6 @@
#include <lib.h>
#include <cpu/cpu.h>
#include <cbmem.h>
-#include <AGESA.h>
#include <cpu/x86/lapic.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index a42ee5c..0e7601a 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -31,7 +31,6 @@
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <Porting.h>
-#include <AGESA.h>
#include <Options.h>
#include <Topology.h>
#include <northbridge/amd/agesa/state_machine.h>
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 5aadccc..8461484 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -816,7 +816,7 @@
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
+ _WRMSR(IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 8b6a8d4..7ca310d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -2148,7 +2148,7 @@
u32 lo, hi;
hi = TestAddr >> 24;
lo = TestAddr << 8;
- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */
+ _WRMSR(IORR0_BASE, lo, hi); /* IORR0 Base */
hi = 0xFF;
lo = 0xFC000800; /* 64MB Mask */
_WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index f6cb285..691e17f 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -27,7 +27,6 @@
#include <cpu/cpu.h>
#include <cbmem.h>
#include <Porting.h>
-#include <AGESA.h>
#include <FieldAccessors.h>
#include <Topology.h>
#include <cpu/x86/lapic.h>
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index fb3610d..05ce428 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -27,7 +27,6 @@
#include <cpu/cpu.h>
#include <cbmem.h>
#include <Porting.h>
-#include <AGESA.h>
#include <FieldAccessors.h>
#include <Topology.h>
#include <cpu/x86/lapic.h>
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 7125e1e..8044c8c 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -29,7 +29,6 @@
#include <cpu/cpu.h>
#include <cbmem.h>
#include <Porting.h>
-#include <AGESA.h>
#include <FieldAccessors.h>
#include <Topology.h>
#include <cpu/x86/lapic.h>
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36
Gerrit-Change-Number: 29352
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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