<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29352">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd: [test] Fix IORR0 MTRR<br><br>Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/amd/agesa/family12/fixme.c<br>M src/cpu/amd/agesa/family14/fixme.c<br>M src/cpu/amd/agesa/family15tn/fixme.c<br>M src/cpu/amd/agesa/family16kb/fixme.c<br>M src/cpu/amd/mtrr/amd_mtrr.c<br>M src/cpu/amd/pi/00630F01/fixme.c<br>M src/cpu/amd/pi/00660F01/fixme.c<br>M src/cpu/amd/pi/00730F01/fixme.c<br>M src/include/cpu/amd/mtrr.h<br>M src/northbridge/amd/agesa/family15tn/northbridge.c<br>M src/northbridge/amd/agesa/family16kb/northbridge.c<br>M src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c<br>M src/northbridge/amd/pi/00630F01/northbridge.c<br>M src/northbridge/amd/pi/00660F01/northbridge.c<br>M src/northbridge/amd/pi/00730F01/northbridge.c<br>16 files changed, 7 insertions(+), 29 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c</span><br><span>index 9df43e5..faaff23 100644</span><br><span>--- a/src/cpu/amd/agesa/family12/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family12/fixme.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span> </span><br><span> void amd_initcpuio(void)</span><br><span>diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c</span><br><span>index a49cefb..4957b07 100644</span><br><span>--- a/src/cpu/amd/agesa/family14/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family14/fixme.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span> </span><br><span> /* Define AMD Ontario APPU SSID/SVID */</span><br><span>diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>index a0ae193..0a02389 100644</span><br><span>--- a/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span> </span><br><span> void amd_initcpuio(void)</span><br><span>diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>index 2d74c7b..d27355d 100644</span><br><span>--- a/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>@@ -17,7 +17,6 @@</span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span> </span><br><span> void amd_initcpuio(void)</span><br><span>diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c</span><br><span>index 8cb6658..3c581f0 100644</span><br><span>--- a/src/cpu/amd/mtrr/amd_mtrr.c</span><br><span>+++ b/src/cpu/amd/mtrr/amd_mtrr.c</span><br><span>@@ -138,7 +138,7 @@</span><br><span> * undefined side effects.</span><br><span> */</span><br><span> msr.lo = msr.hi = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- for (i = IORR_FIRST; i <= IORR_LAST; i++)</span><br><span style="color: hsl(120, 100%, 40%);">+ for (i = IORR0_BASE; i <= IORR1_MASK; i++)</span><br><span> wrmsr(i, msr);</span><br><span> </span><br><span> /* Enable Variable Mtrrs</span><br><span>diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>index ae2a2df..5b3e0c8 100644</span><br><span>--- a/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <Porting.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <amdlib.h></span><br><span> </span><br><span> void amd_initcpuio(void)</span><br><span>diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>index e028b6f..95bee23 100644</span><br><span>--- a/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <Porting.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <amdlib.h></span><br><span> </span><br><span> void amd_initcpuio(void)</span><br><span>diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>index 163066b..f415b36 100644</span><br><span>--- a/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>@@ -18,7 +18,6 @@</span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <Porting.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <amdlib.h></span><br><span> </span><br><span> void amd_initcpuio(void)</span><br><span>diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h</span><br><span>index 46d66f8..d139eca 100644</span><br><span>--- a/src/include/cpu/amd/mtrr.h</span><br><span>+++ b/src/include/cpu/amd/mtrr.h</span><br><span>@@ -1,20 +1,10 @@</span><br><span> #ifndef CPU_AMD_MTRR_H</span><br><span> #define CPU_AMD_MTRR_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/* FIXME</span><br><span style="color: hsl(0, 100%, 40%);">- * Replace</span><br><span style="color: hsl(0, 100%, 40%);">- * #define IORR_FIRST 0xC0010016</span><br><span style="color: hsl(0, 100%, 40%);">- * #define IORR_LAST 0xC0010019</span><br><span style="color: hsl(0, 100%, 40%);">- * with</span><br><span style="color: hsl(0, 100%, 40%);">- * #define IORR0_BASE 0xC0010016</span><br><span style="color: hsl(0, 100%, 40%);">- * #define IORR0_MASK 0xC0010017</span><br><span style="color: hsl(0, 100%, 40%);">- * #define IORR1_BASE 0xC0010018</span><br><span style="color: hsl(0, 100%, 40%);">- * #define IORR1_MASK 0xC0010019</span><br><span style="color: hsl(0, 100%, 40%);">- * those are also defined in vendorcode <AGESA.h> file.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define IORR_FIRST 0xC0010016</span><br><span style="color: hsl(0, 100%, 40%);">-#define IORR_LAST 0xC0010019</span><br><span style="color: hsl(120, 100%, 40%);">+#define IORR0_BASE 0xC0010016</span><br><span style="color: hsl(120, 100%, 40%);">+#define IORR0_MASK 0xC0010017</span><br><span style="color: hsl(120, 100%, 40%);">+#define IORR1_BASE 0xC0010018</span><br><span style="color: hsl(120, 100%, 40%);">+#define IORR1_MASK 0xC0010019</span><br><span> </span><br><span> #define MTRR_READ_MEM (1 << 4)</span><br><span> #define MTRR_WRITE_MEM (1 << 3)</span><br><span>diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c</span><br><span>index 7248eb7..fb2ca61 100644</span><br><span>--- a/src/northbridge/amd/agesa/family15tn/northbridge.c</span><br><span>+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c</span><br><span>@@ -28,7 +28,6 @@</span><br><span> #include <lib.h></span><br><span> #include <cpu/cpu.h></span><br><span> #include <cbmem.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span>diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c</span><br><span>index a42ee5c..0e7601a 100644</span><br><span>--- a/src/northbridge/amd/agesa/family16kb/northbridge.c</span><br><span>+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c</span><br><span>@@ -31,7 +31,6 @@</span><br><span> #include <cpu/amd/msr.h></span><br><span> #include <cpu/amd/mtrr.h></span><br><span> #include <Porting.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <Options.h></span><br><span> #include <Topology.h></span><br><span> #include <northbridge/amd/agesa/state_machine.h></span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c</span><br><span>index 5aadccc..8461484 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c</span><br><span>@@ -816,7 +816,7 @@</span><br><span> u32 lo, hi;</span><br><span> hi = TestAddr >> 24;</span><br><span> lo = TestAddr << 8;</span><br><span style="color: hsl(0, 100%, 40%);">- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ _WRMSR(IORR0_BASE, lo, hi); /* IORR0 Base */</span><br><span> hi = 0xFF;</span><br><span> lo = 0xFC000800; /* 64MB Mask */</span><br><span> _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>index 8b6a8d4..7ca310d 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>@@ -2148,7 +2148,7 @@</span><br><span> u32 lo, hi;</span><br><span> hi = TestAddr >> 24;</span><br><span> lo = TestAddr << 8;</span><br><span style="color: hsl(0, 100%, 40%);">- _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */</span><br><span style="color: hsl(120, 100%, 40%);">+ _WRMSR(IORR0_BASE, lo, hi); /* IORR0 Base */</span><br><span> hi = 0xFF;</span><br><span> lo = 0xFC000800; /* 64MB Mask */</span><br><span> _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */</span><br><span>diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c</span><br><span>index f6cb285..691e17f 100644</span><br><span>--- a/src/northbridge/amd/pi/00630F01/northbridge.c</span><br><span>+++ b/src/northbridge/amd/pi/00630F01/northbridge.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #include <cpu/cpu.h></span><br><span> #include <cbmem.h></span><br><span> #include <Porting.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <FieldAccessors.h></span><br><span> #include <Topology.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span>diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c</span><br><span>index fb3610d..05ce428 100644</span><br><span>--- a/src/northbridge/amd/pi/00660F01/northbridge.c</span><br><span>+++ b/src/northbridge/amd/pi/00660F01/northbridge.c</span><br><span>@@ -27,7 +27,6 @@</span><br><span> #include <cpu/cpu.h></span><br><span> #include <cbmem.h></span><br><span> #include <Porting.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <FieldAccessors.h></span><br><span> #include <Topology.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span>diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c</span><br><span>index 7125e1e..8044c8c 100644</span><br><span>--- a/src/northbridge/amd/pi/00730F01/northbridge.c</span><br><span>+++ b/src/northbridge/amd/pi/00730F01/northbridge.c</span><br><span>@@ -29,7 +29,6 @@</span><br><span> #include <cpu/cpu.h></span><br><span> #include <cbmem.h></span><br><span> #include <Porting.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <AGESA.h></span><br><span> #include <FieldAccessors.h></span><br><span> #include <Topology.h></span><br><span> #include <cpu/x86/lapic.h></span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29352">change 29352</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 </div>
<div style="display:none"> Gerrit-Change-Number: 29352 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>