[coreboot-gerrit] Change in coreboot[master]: /soc/intel:Update tcc offset for fleex
John Su (Code Review)
gerrit at coreboot.org
Tue Oct 30 03:29:56 CET 2018
John Su has uploaded this change for review. ( https://review.coreboot.org/29351
Change subject: /soc/intel:Update tcc offset for fleex
......................................................................
/soc/intel:Update tcc offset for fleex
Change tcc offset from 0 to 10.
Refer to b:117789732#comment20.
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Signed-off-by: John Su <john_su at compal.corp-partner.google.com>
---
M src/soc/intel/apollolake/romstage.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29351/1
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index d2ec6c1..eeb0c12 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -198,6 +198,12 @@
s3wake = pmc_fill_power_state(ps) == ACPI_S3;
fsp_memory_init(s3wake);
+ /* Set TCC offset */
+ msr_t msr;
+ msr.lo = 0xa690000;
+ msr.hi = 0x0;
+ wrmsr(0x1a2, msr);
+
if (punit_init())
set_max_freq();
else
--
To view, visit https://review.coreboot.org/29351
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Gerrit-Change-Number: 29351
Gerrit-PatchSet: 1
Gerrit-Owner: John Su <john_su at compal.corp-partner.google.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181030/7a84e7b4/attachment.html>
More information about the coreboot-gerrit
mailing list