[coreboot-gerrit] Change in coreboot[master]: {cpu, drivers, sb}/amd: Replace MTRR addresses with macros
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue Oct 23 17:12:03 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29243
Change subject: {cpu,drivers,sb}/amd: Replace MTRR addresses with macros
......................................................................
{cpu,drivers,sb}/amd: Replace MTRR addresses with macros
Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/cpu/amd/agesa/family12/fixme.c
M src/cpu/amd/agesa/family14/fixme.c
M src/cpu/amd/agesa/family15tn/fixme.c
M src/cpu/amd/agesa/family16kb/fixme.c
M src/cpu/amd/pi/00630F01/fixme.c
M src/cpu/amd/pi/00660F01/fixme.c
M src/cpu/amd/pi/00730F01/fixme.c
M src/drivers/amd/agesa/s3_mtrr.c
M src/southbridge/amd/rs780/gfx.c
M src/southbridge/amd/sr5650/sr5650.c
10 files changed, 21 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/1
diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c
index e97a819..9df43e5 100644
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -40,7 +41,7 @@
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00DFFF00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 978c25f..a49cefb 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -51,7 +52,7 @@
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; // last address before non-posted range
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg;
diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c
index 7e493f9..a0ae193 100644
--- a/src/cpu/amd/agesa/family15tn/fixme.c
+++ b/src/cpu/amd/agesa/family15tn/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -47,7 +48,7 @@
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index c761d6d..2d74c7b 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <AGESA.h>
#include "amdlib.h"
@@ -47,7 +48,7 @@
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c
index 11cab62..ae2a2df 100644
--- a/src/cpu/amd/pi/00630F01/fixme.c
+++ b/src/cpu/amd/pi/00630F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -52,7 +53,7 @@
/* last address before non-posted range */
PciData = 0x00FECF00;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index ee8728d..e028b6f 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -51,7 +52,7 @@
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c
index 4350572..163066b 100644
--- a/src/cpu/amd/pi/00730F01/fixme.c
+++ b/src/cpu/amd/pi/00730F01/fixme.c
@@ -15,6 +15,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
+#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
@@ -51,7 +52,7 @@
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);
+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c
index 531ad45..4df7b05 100644
--- a/src/drivers/amd/agesa/s3_mtrr.c
+++ b/src/drivers/amd/agesa/s3_mtrr.c
@@ -61,9 +61,9 @@
/* SYSCFG_MSR */
write_mtrr(&nvram_pos, SYSCFG_MSR);
/* TOM */
- write_mtrr(&nvram_pos, 0xC001001A);
+ write_mtrr(&nvram_pos, TOP_MEM);
/* TOM2 */
- write_mtrr(&nvram_pos, 0xC001001D);
+ write_mtrr(&nvram_pos, TOP_MEM2);
*mtrr_store_size = nvram_pos - (u8*) mtrr_store;
}
diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c
index 43bfb02..d71d646 100644
--- a/src/southbridge/amd/rs780/gfx.c
+++ b/src/southbridge/amd/rs780/gfx.c
@@ -34,6 +34,7 @@
#include <device/pci_ops.h>
#include <delay.h>
#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
#include "rs780.h"
/* Trust the original resource allocation. Don't do it again. */
@@ -762,11 +763,11 @@
printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);
/* The system top memory in 780. */
- sysmem = rdmsr(0xc001001a);
+ sysmem = rdmsr(TOP_MEM);
printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
pci_write_config32(nb_dev, 0x90, sysmem.lo);
- sysmem = rdmsr(0xc001001D);
+ sysmem = rdmsr(TOP_MEM);
printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
htiu_write_index(nb_dev, 0x31, sysmem.hi);
htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c
index 1e85c48..0f8b265 100644
--- a/src/southbridge/amd/sr5650/sr5650.c
+++ b/src/southbridge/amd/sr5650/sr5650.c
@@ -304,11 +304,11 @@
msr_t sysmem;
/* The system top memory in SR56X0. */
- sysmem = rdmsr(0xc001001A);
+ sysmem = rdmsr(TOP_MEM);
printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
pci_write_config32(nb_dev, 0x90, sysmem.lo);
- sysmem = rdmsr(0xc001001D);
+ sysmem = rdmsr(TOP_MEM2);
printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
htiu_write_index(nb_dev, 0x31, sysmem.hi);
htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b
Gerrit-Change-Number: 29243
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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