<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29243">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">{cpu,drivers,sb}/amd: Replace MTRR addresses with macros<br><br>Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/cpu/amd/agesa/family12/fixme.c<br>M src/cpu/amd/agesa/family14/fixme.c<br>M src/cpu/amd/agesa/family15tn/fixme.c<br>M src/cpu/amd/agesa/family16kb/fixme.c<br>M src/cpu/amd/pi/00630F01/fixme.c<br>M src/cpu/amd/pi/00660F01/fixme.c<br>M src/cpu/amd/pi/00730F01/fixme.c<br>M src/drivers/amd/agesa/s3_mtrr.c<br>M src/southbridge/amd/rs780/gfx.c<br>M src/southbridge/amd/sr5650/sr5650.c<br>10 files changed, 21 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29243/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c</span><br><span>index e97a819..9df43e5 100644</span><br><span>--- a/src/cpu/amd/agesa/family12/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family12/fixme.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span>@@ -40,7 +41,7 @@</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);</span><br><span> PciData = 0x00DFFF00;</span><br><span> LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);</span><br><span> MsrReg = (MsrReg >> 8) | 3;</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);</span><br><span> PciData = (UINT32) MsrReg;</span><br><span>diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c</span><br><span>index 978c25f..a49cefb 100644</span><br><span>--- a/src/cpu/amd/agesa/family14/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family14/fixme.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span>@@ -51,7 +52,7 @@</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);</span><br><span> PciData = 0x00FECF00; // last address before non-posted range</span><br><span> LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);</span><br><span> MsrReg = (MsrReg >> 8) | 3;</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);</span><br><span> PciData = (UINT32) MsrReg;</span><br><span>diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>index 7e493f9..a0ae193 100644</span><br><span>--- a/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family15tn/fixme.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span>@@ -47,7 +48,7 @@</span><br><span> PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);</span><br><span> PciData = 0x00FECF00; /* last address before non-posted range */</span><br><span> LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);</span><br><span> MsrReg = (MsrReg >> 8) | 3;</span><br><span> PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);</span><br><span> PciData = (UINT32)MsrReg;</span><br><span>diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>index c761d6d..2d74c7b 100644</span><br><span>--- a/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>+++ b/src/cpu/amd/agesa/family16kb/fixme.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <AGESA.h></span><br><span> #include "amdlib.h"</span><br><span>@@ -47,7 +48,7 @@</span><br><span> PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);</span><br><span> PciData = 0x00FECF00; /* last address before non-posted range */</span><br><span> LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);</span><br><span> MsrReg = (MsrReg >> 8) | 3;</span><br><span> PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);</span><br><span> PciData = (UINT32)MsrReg;</span><br><span>diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>index 11cab62..ae2a2df 100644</span><br><span>--- a/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00630F01/fixme.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <Porting.h></span><br><span> #include <AGESA.h></span><br><span>@@ -52,7 +53,7 @@</span><br><span> /* last address before non-posted range */</span><br><span> PciData = 0x00FECF00;</span><br><span> LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);</span><br><span> MsrReg = (MsrReg >> 8) | 3;</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);</span><br><span> PciData = (UINT32)MsrReg;</span><br><span>diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>index ee8728d..e028b6f 100644</span><br><span>--- a/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00660F01/fixme.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <Porting.h></span><br><span> #include <AGESA.h></span><br><span>@@ -51,7 +52,7 @@</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);</span><br><span> PciData = 0x00FECF00; /* last address before non-posted range */</span><br><span> LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);</span><br><span> MsrReg = (MsrReg >> 8) | 3;</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);</span><br><span> PciData = (UINT32)MsrReg;</span><br><span>diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>index 4350572..163066b 100644</span><br><span>--- a/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>+++ b/src/cpu/amd/pi/00730F01/fixme.c</span><br><span>@@ -15,6 +15,7 @@</span><br><span> </span><br><span> #include <cpu/x86/mtrr.h></span><br><span> #include <cpu/amd/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include <northbridge/amd/agesa/agesa_helper.h></span><br><span> #include <Porting.h></span><br><span> #include <AGESA.h></span><br><span>@@ -51,7 +52,7 @@</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);</span><br><span> PciData = 0x00FECF00; /* last address before non-posted range */</span><br><span> LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);</span><br><span style="color: hsl(0, 100%, 40%);">- LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader);</span><br><span style="color: hsl(120, 100%, 40%);">+ LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);</span><br><span> MsrReg = (MsrReg >> 8) | 3;</span><br><span> PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);</span><br><span> PciData = (UINT32)MsrReg;</span><br><span>diff --git a/src/drivers/amd/agesa/s3_mtrr.c b/src/drivers/amd/agesa/s3_mtrr.c</span><br><span>index 531ad45..4df7b05 100644</span><br><span>--- a/src/drivers/amd/agesa/s3_mtrr.c</span><br><span>+++ b/src/drivers/amd/agesa/s3_mtrr.c</span><br><span>@@ -61,9 +61,9 @@</span><br><span> /* SYSCFG_MSR */</span><br><span> write_mtrr(&nvram_pos, SYSCFG_MSR);</span><br><span> /* TOM */</span><br><span style="color: hsl(0, 100%, 40%);">- write_mtrr(&nvram_pos, 0xC001001A);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_mtrr(&nvram_pos, TOP_MEM);</span><br><span> /* TOM2 */</span><br><span style="color: hsl(0, 100%, 40%);">- write_mtrr(&nvram_pos, 0xC001001D);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_mtrr(&nvram_pos, TOP_MEM2);</span><br><span> </span><br><span> *mtrr_store_size = nvram_pos - (u8*) mtrr_store;</span><br><span> }</span><br><span>diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c</span><br><span>index 43bfb02..d71d646 100644</span><br><span>--- a/src/southbridge/amd/rs780/gfx.c</span><br><span>+++ b/src/southbridge/amd/rs780/gfx.c</span><br><span>@@ -34,6 +34,7 @@</span><br><span> #include <device/pci_ops.h></span><br><span> #include <delay.h></span><br><span> #include <cpu/x86/msr.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/amd/mtrr.h></span><br><span> #include "rs780.h"</span><br><span> </span><br><span> /* Trust the original resource allocation. Don't do it again. */</span><br><span>@@ -762,11 +763,11 @@</span><br><span> printk(BIOS_DEBUG, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev);</span><br><span> </span><br><span> /* The system top memory in 780. */</span><br><span style="color: hsl(0, 100%, 40%);">- sysmem = rdmsr(0xc001001a);</span><br><span style="color: hsl(120, 100%, 40%);">+ sysmem = rdmsr(TOP_MEM);</span><br><span> printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);</span><br><span> pci_write_config32(nb_dev, 0x90, sysmem.lo);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- sysmem = rdmsr(0xc001001D);</span><br><span style="color: hsl(120, 100%, 40%);">+ sysmem = rdmsr(TOP_MEM);</span><br><span> printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);</span><br><span> htiu_write_index(nb_dev, 0x31, sysmem.hi);</span><br><span> htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);</span><br><span>diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>index 1e85c48..0f8b265 100644</span><br><span>--- a/src/southbridge/amd/sr5650/sr5650.c</span><br><span>+++ b/src/southbridge/amd/sr5650/sr5650.c</span><br><span>@@ -304,11 +304,11 @@</span><br><span> msr_t sysmem;</span><br><span> </span><br><span> /* The system top memory in SR56X0. */</span><br><span style="color: hsl(0, 100%, 40%);">- sysmem = rdmsr(0xc001001A);</span><br><span style="color: hsl(120, 100%, 40%);">+ sysmem = rdmsr(TOP_MEM);</span><br><span> printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);</span><br><span> pci_write_config32(nb_dev, 0x90, sysmem.lo);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- sysmem = rdmsr(0xc001001D);</span><br><span style="color: hsl(120, 100%, 40%);">+ sysmem = rdmsr(TOP_MEM2);</span><br><span> printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);</span><br><span> htiu_write_index(nb_dev, 0x31, sysmem.hi);</span><br><span> htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29243">change 29243</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7e8de35dcdad52bb311b34bfa9b272d17ed3186b </div>
<div style="display:none"> Gerrit-Change-Number: 29243 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>