[coreboot-gerrit] Change in coreboot[master]: mb/lenovo/*/romstage: Use macros instead of magic numbers

[Peter Lemenkov (Code Review)]

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/29208


Change subject: mb/lenovo/*/romstage: Use macros instead of magic numbers
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mb/lenovo/*/romstage: Use macros instead of magic numbers

Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead.

Please, take a look at the following diff:

        /* Set up I/O Trap #0 for 0xfe00 (SMIC) */
        RCBA32(0x1e84) = 0x00020001;
-       RCBA32(0x1e80) = 0x0000fe01;
+       RCBA32(IOTR0) = 0x0000fe01;

IOTR[0123] is a 64-bit width value. Unfortunately, we don't have RCBA64 macro
yet so we have to use two RCBA32's here.

lemenkov ~/work/coreboot (git::master): grep -R IOTR0 src/southbridge/
src/southbridge/intel/i82801gx/i82801gx.h:#define IOTR0		0x1e80	/* 64bit */
src/southbridge/intel/ibexpeak/pch.h:#define IOTR0		0x1e80	/* 64bit */
src/southbridge/intel/bd82x6x/pch.h:#define IOTR0		0x1e80	/* 64bit */
src/southbridge/intel/fsp_bd82x6x/pch.h:#define IOTR0		0x1e80	/* 64bit */
src/southbridge/intel/lynxpoint/pch.h:#define IOTR0		0x1e80	/* 64bit */
lemenkov ~/work/coreboot (git::master):

Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57
Signed-off-by: Peter Lemenkov <lemenkov at gmail.com>
---
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/x60/romstage.c
2 files changed, 8 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29208/1

diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index e4a8efb..9d3cab9 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -76,8 +76,8 @@
 static void rcba_config(void)
 {
 	/* Set up virtual channel 0 */
-	RCBA32(0x0014) = 0x80000001;
-	RCBA32(0x001c) = 0x03128010;
+	RCBA32(V0CTL) = 0x80000001;
+	RCBA32(V1CAP) = 0x03128010;
 
 	/* Device 1f interrupt pin register */
 	RCBA32(D31IP) = 0x00001230;
@@ -104,11 +104,11 @@
 
 	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 	RCBA32(0x1e84) = 0x00020001;
-	RCBA32(0x1e80) = 0x0000fe01;
+	RCBA32(IOTR0) = 0x0000fe01;
 
 	/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
 	RCBA32(0x1e9c) = 0x000200f0;
-	RCBA32(0x1e98) = 0x000c0801;
+	RCBA32(IOTR3) = 0x000c0801;
 }
 
 static void early_ich7_init(void)
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 81ee5da..229975b 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -75,8 +75,8 @@
 static void rcba_config(void)
 {
 	/* Set up virtual channel 0 */
-	RCBA32(0x0014) = 0x80000001;
-	RCBA32(0x001c) = 0x03128010;
+	RCBA32(V0CTL) = 0x80000001;
+	RCBA32(V1CAP) = 0x03128010;
 
 	/* Device 1f interrupt pin register */
 	RCBA32(D31IP) = 0x00001230;
@@ -103,11 +103,11 @@
 
 	/* Set up I/O Trap #0 for 0xfe00 (SMIC) */
 	RCBA32(0x1e84) = 0x00020001;
-	RCBA32(0x1e80) = 0x0000fe01;
+	RCBA32(IOTR0) = 0x0000fe01;
 
 	/* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
 	RCBA32(0x1e9c) = 0x000200f0;
-	RCBA32(0x1e98) = 0x000c0801;
+	RCBA32(IOTR3) = 0x000c0801;
 }
 
 static void early_ich7_init(void)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icf185c77ede5a258fe37be9e772be6804d014b57
Gerrit-Change-Number: 29208
Gerrit-PatchSet: 1
Gerrit-Owner: Peter Lemenkov <lemenkov at gmail.com>
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