[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/fast_spi: ensure flash is useable

[Christian Gmeiner (Code Review)]

Christian Gmeiner has uploaded this change for review. ( https://review.coreboot.org/29159


Change subject: soc/intel/common/fast_spi: ensure flash is useable
......................................................................

soc/intel/common/fast_spi: ensure flash is useable

During bootblock execution fast_spi_init() get called which disables the
BIOS write protect and enables prefetching and caching.

bios_cntl: get changed from 0x28 to 0x9

Later in ramstage the mrc cache code detects the internal fast spi interface
and might want to update the conent of that region. At this stage the bios_cntl
register has a value of 0x29. This leads to following error:

MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
SPI Transaction Error at Flash Offset a50000 HSFSTS = 0x01046003
REGF metadata allocation failed: 392 data blocks 4096 total blocks

I tried to figure out why and where bios_cntl got changed but I did not found anything.
With this change mrc cache works expected.

FMAP: Found "FLASH" version 1.1 at a40000.
FMAP: base = ff000000 size = 1000000 #areas = 4
FMAP: area RW_MRC_CACHE found @ a50000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
MRC: no data in 'RW_MRC_CACHE'
MRC: cache data 'RW_MRC_CACHE' needs update.
MRC: Could not find region 'UNIFIED_MRC_CACHE'
FMAP: area RW_MRC_CACHE found @ a50000 (65536 bytes)
MRC: NOT enabling PRR for 'RW_MRC_CACHE'.
BS: BS_DEV_ENUMERATE times (us): entry 0 run 593 exit 8306

Change-Id: If2ca62fcdf76c33fab22f81e3acb91b3a054c8e5
Signed-off-by: Christian Gmeiner <christian.gmeiner at gmail.com>
---
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
1 file changed, 3 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29159/1

diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
index 4579b19..7f627af 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
@@ -292,6 +292,9 @@
 	BOILERPLATE_CREATE_CTX(ctx);
 	uint32_t flash_bits;
 
+	/* Ensure fast_spi is correctly setup. */
+	fast_spi_init();
+
 	/*
 	 * bytes = (bits + 1) / 8;
 	 * But we need to do the addition in a way which doesn't overflow for

-- 
To view, visit https://review.coreboot.org/29159
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If2ca62fcdf76c33fab22f81e3acb91b3a054c8e5
Gerrit-Change-Number: 29159
Gerrit-PatchSet: 1
Gerrit-Owner: Christian Gmeiner <christian.gmeiner at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20181017/6375b1c9/attachment.html>