[coreboot-gerrit] Change in coreboot[master]: sb/amd/pi/hudson: Add SPI controller support

Mon Oct 15 10:05:10 CEST 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28719 )

Change subject: sb/amd/pi/hudson: Add SPI controller support
......................................................................

Patch Set 4:

(24 comments)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h
File src/southbridge/amd/pi/hudson/pci_devs.h:

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@34
PS4, Line 34: #define XHCI_PCIDEV		_PCI_DEV(XHCI_DEV,XHCI_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@40
PS4, Line 40: #define XHCI2_PCIDEV		_PCI_DEV(XHCI2_DEV,XHCI2_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@49
PS4, Line 49: #define SATA_PCIDEV		_PCI_DEV(SATA_DEV,SATA_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@65
PS4, Line 65: #define OHCI1_PCIDEV		_PCI_DEV(OHCI1_DEV,OHCI1_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@66
PS4, Line 66: #define OHCI2_PCIDEV		_PCI_DEV(OHCI2_DEV,OHCI2_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@67
PS4, Line 67: #define OHCI3_PCIDEV		_PCI_DEV(OHCI3_DEV,OHCI3_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@68
PS4, Line 68: #define OHCI4_PCIDEV		_PCI_DEV(OHCI4_DEV,OHCI4_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@81
PS4, Line 81: #define EHCI1_PCIDEV		_PCI_DEV(EHCI1_DEV,EHCI1_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@82
PS4, Line 82: #define EHCI2_PCIDEV		_PCI_DEV(EHCI2_DEV,EHCI2_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@83
PS4, Line 83: #define EHCI3_PCIDEV		_PCI_DEV(EHCI3_DEV,EHCI3_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@90
PS4, Line 90: #define SMBUS_PCIDEV		_PCI_DEV(SMBUS_DEV,SMBUS_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@98
PS4, Line 98: #define IDE_PCIDEV		_PCI_DEV(IDE_DEV,IDE_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@106
PS4, Line 106: #define HDA_PCIDEV		_PCI_DEV(HDA_DEV,HDA_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@114
PS4, Line 114: #define LPC_PCIDEV		_PCI_DEV(LPC_DEV,LPC_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@121
PS4, Line 121: #define SB_PCI_PORT_PCIDEV	_PCI_DEV(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@128
PS4, Line 128: #define SD_PCIDEV		_PCI_DEV(SD_DEV,SD_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@145
PS4, Line 145: #define SB_PCIE_PORT1_PCIDEV	_PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@146
PS4, Line 146: #define SB_PCIE_PORT2_PCIDEV	_PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@147
PS4, Line 147: #define SB_PCIE_PORT3_PCIDEV	_PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/pci_devs.h@148
PS4, Line 148: #define SB_PCIE_PORT4_PCIDEV	_PCI_DEV(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c
File src/southbridge/amd/pi/hudson/spi.c:

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c@117
PS4, Line 117: 	while ((spi_read8(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) &&
trailing statements should be on next line

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c@165
PS4, Line 165: 	for (count = 0; count < bytesout; count++, dout++) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c@174
PS4, Line 174: 	for (count = 0; count < bytesout; count++) {
braces {} are not necessary for single statement blocks

https://review.coreboot.org/#/c/28719/4/src/southbridge/amd/pi/hudson/spi.c@178
PS4, Line 178: 	for (count = 0; count < bytesin; count++, din++) {
braces {} are not necessary for single statement blocks

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Icc6feb433a19337e09fc394cbf30288f53b195dd
Gerrit-Change-Number: 28719
Gerrit-PatchSet: 4
Gerrit-Owner: Michał Żygowski <michal.zygowski at 3mdeb.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner at chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki at gmail.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski at 3mdeb.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Piotr Król <piotr.krol at 3mdeb.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer at coreboot.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Marc Jones <marc at marcjonesconsulting.com>
Gerrit-Comment-Date: Mon, 15 Oct 2018 08:05:10 +0000
Gerrit-HasComments: Yes
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