[coreboot-gerrit] Change in coreboot[master]: amd/stoneyridge: Convert hex definitions to lower case
Martin Roth (Code Review)
gerrit at coreboot.org
Fri Oct 12 17:13:35 CEST 2018
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29009 )
Change subject: amd/stoneyridge: Convert hex definitions to lower case
......................................................................
amd/stoneyridge: Convert hex definitions to lower case
Match the rest of the soc/stoneyridge source.
Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e
Signed-off-by: Marshall Dawson <marshalldawson3rd at gmail.com>
Reviewed-on: https://review.coreboot.org/29009
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/enable_usbdebug.c
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/amd/stoneyridge/southbridge.c
4 files changed, 24 insertions(+), 24 deletions(-)
Approvals:
build bot (Jenkins): Verified
Richard Spiegel: Looks good to me, approved
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 3881042..d56e105 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -53,7 +53,7 @@
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 0, 2, 0);
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, 0xF);
+ current, 0, 9, 9, 0xf);
/* create all subtables for processors */
current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,
diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c
index 81f60f0..5220457 100644
--- a/src/soc/amd/stoneyridge/enable_usbdebug.c
+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c
@@ -25,8 +25,8 @@
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)
{
/* Enable all of the USB controllers */
- outb(0xEF, PM_INDEX);
- outb(0x7F, PM_DATA);
+ outb(0xef, PM_INDEX);
+ outb(0x7f, PM_DATA);
if (hcd_idx == 3)
return PCI_DEV(0, 0x16, 0);
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index e7a8cc3..c50733b 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -232,7 +232,7 @@
#define SPI_CMD_TRIGGER 0x47
#define SPI_CMD_TRIGGER_EXECUTE (BIT(7))
#define SPI_TX_BYTE_COUNT 0x48
-#define SPI_RX_BYTE_COUNT 0x4B
+#define SPI_RX_BYTE_COUNT 0x4b
#define SPI_STATUS 0x4c
#define SPI_DONE_BYTE_COUNT_SHIFT 0
#define SPI_DONE_BYTE_COUNT_MASK 0xff
@@ -280,7 +280,7 @@
#define TOGGLE_ALL_PWR_GOOD BIT(1)
#define XHCI_PM_INDIRECT_INDEX 0x48
-#define XHCI_PM_INDIRECT_DATA 0x4C
+#define XHCI_PM_INDIRECT_DATA 0x4c
#define XHCI_OVER_CURRENT_CONTROL 0x30
#define EHCI_OVER_CURRENT_CONTROL 0x70
@@ -316,15 +316,15 @@
/* FCH AOAC Registers 0xfed81e00 */
#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
-#define FCH_AOAC_D3_CONTROL_I2C0 0x4A
-#define FCH_AOAC_D3_CONTROL_I2C1 0x4C
-#define FCH_AOAC_D3_CONTROL_I2C2 0x4E
+#define FCH_AOAC_D3_CONTROL_I2C0 0x4a
+#define FCH_AOAC_D3_CONTROL_I2C1 0x4c
+#define FCH_AOAC_D3_CONTROL_I2C2 0x4e
#define FCH_AOAC_D3_CONTROL_I2C3 0x50
#define FCH_AOAC_D3_CONTROL_UART0 0x56
#define FCH_AOAC_D3_CONTROL_UART1 0x58
#define FCH_AOAC_D3_CONTROL_AMBA 0x62
#define FCH_AOAC_D3_CONTROL_USB2 0x64
-#define FCH_AOAC_D3_CONTROL_USB3 0x6E
+#define FCH_AOAC_D3_CONTROL_USB3 0x6e
/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
#define FCH_AOAC_DEVICE_STATE BIT(2)
@@ -335,15 +335,15 @@
#define FCH_AOAC_IS_SW_CONTROL BIT(7)
#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
-#define FCH_AOAC_D3_STATE_I2C0 0x4B
-#define FCH_AOAC_D3_STATE_I2C1 0x4D
-#define FCH_AOAC_D3_STATE_I2C2 0x4F
+#define FCH_AOAC_D3_STATE_I2C0 0x4b
+#define FCH_AOAC_D3_STATE_I2C1 0x4d
+#define FCH_AOAC_D3_STATE_I2C2 0x4f
#define FCH_AOAC_D3_STATE_I2C3 0x51
#define FCH_AOAC_D3_STATE_UART0 0x57
#define FCH_AOAC_D3_STATE_UART1 0x59
#define FCH_AOAC_D3_STATE_AMBA 0x63
#define FCH_AOAC_D3_STATE_USB2 0x65
-#define FCH_AOAC_D3_STATE_USB3 0x6F
+#define FCH_AOAC_D3_STATE_USB3 0x6f
/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
#define FCH_AOAC_PWR_RST_STATE BIT(0)
#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
@@ -373,20 +373,20 @@
#define CG1PLL_SPREAD_SPECTRUM_ENABLE BIT(0)
#define MISC_CGPLL_CONFIG3 0x10
#define CG1PLL_REFDIV_SHIFT 0
-#define CG1PLL_REFDIV_MASK (0x3FF << CG1PLL_REFDIV_SHIFT)
+#define CG1PLL_REFDIV_MASK (0x3ff << CG1PLL_REFDIV_SHIFT)
#define CG1PLL_FBDIV_SHIFT 10
-#define CG1PLL_FBDIV_MASK (0xFFF << CG1PLL_FBDIV_SHIFT)
+#define CG1PLL_FBDIV_MASK (0xfff << CG1PLL_FBDIV_SHIFT)
#define MISC_CGPLL_CONFIG4 0x14
#define CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT 0
-#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
+#define CG1PLL_SS_STEP_SIZE_DSFRAC_MASK (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)
#define CG1PLL_SS_AMOUNT_DSFRAC_SHIFT 16
-#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
+#define CG1PLL_SS_AMOUNT_DSFRAC_MASK (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)
#define MISC_CGPLL_CONFIG5 0x18
#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT 8
-#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
-#define MISC_CGPLL_CONFIG6 0x1C
+#define CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)
+#define MISC_CGPLL_CONFIG6 0x1c
#define CG1PLL_LF_MODE_SHIFT 9
-#define CG1PLL_LF_MODE_MASK (0x1FF << CG1PLL_LF_MODE_SHIFT)
+#define CG1PLL_LF_MODE_MASK (0x1ff << CG1PLL_LF_MODE_SHIFT)
#define MISC_CLK_CNTL1 0x40
#define CG1PLL_FBDIV_TEST BIT(26)
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 763ddd7..7f0318a 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -578,14 +578,14 @@
uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);
cfg6 &= ~CG1PLL_LF_MODE_MASK;
- cfg6 |= (0x0F8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
+ cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;
misc_write32(MISC_CGPLL_CONFIG6, cfg6);
uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);
cfg3 &= ~CG1PLL_REFDIV_MASK;
cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;
cfg3 &= ~CG1PLL_FBDIV_MASK;
- cfg3 |= (0x04B << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
+ cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;
misc_write32(MISC_CGPLL_CONFIG3, cfg3);
uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);
@@ -595,9 +595,9 @@
uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);
cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK;
- cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK;
+ cfg4 |= (0xd000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK;
cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;
- cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;
+ cfg4 |= (0x02d5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;
misc_write32(MISC_CGPLL_CONFIG4, cfg4);
rstcfg |= TOGGLE_ALL_PWR_GOOD;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e
Gerrit-Change-Number: 29009
Gerrit-PatchSet: 2
Gerrit-Owner: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd at gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Richard Spiegel <richard.spiegel at silverbackltd.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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