<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/29009">View Change</a></p><div style="white-space:pre-wrap">Approvals:
  build bot (Jenkins): Verified
  Richard Spiegel: Looks good to me, approved

</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Convert hex definitions to lower case<br><br>Match the rest of the soc/stoneyridge source.<br><br>Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>Reviewed-on: https://review.coreboot.org/29009<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com><br>---<br>M src/soc/amd/stoneyridge/acpi.c<br>M src/soc/amd/stoneyridge/enable_usbdebug.c<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>M src/soc/amd/stoneyridge/southbridge.c<br>4 files changed, 24 insertions(+), 24 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c</span><br><span>index 3881042..d56e105 100644</span><br><span>--- a/src/soc/amd/stoneyridge/acpi.c</span><br><span>+++ b/src/soc/amd/stoneyridge/acpi.c</span><br><span>@@ -53,7 +53,7 @@</span><br><span>    current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span>                                          current, 0, 0, 2, 0);</span><br><span>        current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)</span><br><span style="color: hsl(0, 100%, 40%);">-                                             current, 0, 9, 9, 0xF);</span><br><span style="color: hsl(120, 100%, 40%);">+                                               current, 0, 9, 9, 0xf);</span><br><span> </span><br><span>  /* create all subtables for processors */</span><br><span>    current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current,</span><br><span>diff --git a/src/soc/amd/stoneyridge/enable_usbdebug.c b/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>index 81f60f0..5220457 100644</span><br><span>--- a/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>+++ b/src/soc/amd/stoneyridge/enable_usbdebug.c</span><br><span>@@ -25,8 +25,8 @@</span><br><span> pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx)</span><br><span> {</span><br><span>      /* Enable all of the USB controllers */</span><br><span style="color: hsl(0, 100%, 40%);">- outb(0xEF, PM_INDEX);</span><br><span style="color: hsl(0, 100%, 40%);">-   outb(0x7F, PM_DATA);</span><br><span style="color: hsl(120, 100%, 40%);">+  outb(0xef, PM_INDEX);</span><br><span style="color: hsl(120, 100%, 40%);">+ outb(0x7f, PM_DATA);</span><br><span> </span><br><span>     if (hcd_idx == 3)</span><br><span>            return PCI_DEV(0, 0x16, 0);</span><br><span>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>index e7a8cc3..c50733b 100644</span><br><span>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h</span><br><span>@@ -232,7 +232,7 @@</span><br><span> #define SPI_CMD_TRIGGER           0x47</span><br><span> #define   SPI_CMD_TRIGGER_EXECUTE       (BIT(7))</span><br><span> #define SPI_TX_BYTE_COUNT           0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define SPI_RX_BYTE_COUNT           0x4B</span><br><span style="color: hsl(120, 100%, 40%);">+#define SPI_RX_BYTE_COUNT         0x4b</span><br><span> #define SPI_STATUS                      0x4c</span><br><span> #define   SPI_DONE_BYTE_COUNT_SHIFT     0</span><br><span> #define   SPI_DONE_BYTE_COUNT_MASK 0xff</span><br><span>@@ -280,7 +280,7 @@</span><br><span> #define   TOGGLE_ALL_PWR_GOOD             BIT(1)</span><br><span> </span><br><span> #define XHCI_PM_INDIRECT_INDEX            0x48</span><br><span style="color: hsl(0, 100%, 40%);">-#define XHCI_PM_INDIRECT_DATA               0x4C</span><br><span style="color: hsl(120, 100%, 40%);">+#define XHCI_PM_INDIRECT_DATA             0x4c</span><br><span> #define   XHCI_OVER_CURRENT_CONTROL     0x30</span><br><span> #define EHCI_OVER_CURRENT_CONTROL       0x70</span><br><span> </span><br><span>@@ -316,15 +316,15 @@</span><br><span> </span><br><span> /* FCH AOAC Registers 0xfed81e00 */</span><br><span> #define FCH_AOAC_D3_CONTROL_CLK_GEN      0x40</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_CONTROL_I2C0    0x4A</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_CONTROL_I2C1    0x4C</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_CONTROL_I2C2    0x4E</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_CONTROL_I2C0  0x4a</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_CONTROL_I2C1  0x4c</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_CONTROL_I2C2  0x4e</span><br><span> #define FCH_AOAC_D3_CONTROL_I2C3        0x50</span><br><span> #define FCH_AOAC_D3_CONTROL_UART0       0x56</span><br><span> #define FCH_AOAC_D3_CONTROL_UART1       0x58</span><br><span> #define FCH_AOAC_D3_CONTROL_AMBA        0x62</span><br><span> #define FCH_AOAC_D3_CONTROL_USB2        0x64</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_CONTROL_USB3    0x6E</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_CONTROL_USB3  0x6e</span><br><span> /* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */</span><br><span> #define   FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))</span><br><span> #define   FCH_AOAC_DEVICE_STATE            BIT(2)</span><br><span>@@ -335,15 +335,15 @@</span><br><span> #define   FCH_AOAC_IS_SW_CONTROL      BIT(7)</span><br><span> </span><br><span> #define FCH_AOAC_D3_STATE_CLK_GEN 0x41</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_STATE_I2C0              0x4B</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_STATE_I2C1              0x4D</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_STATE_I2C2              0x4F</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_STATE_I2C0            0x4b</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_STATE_I2C1            0x4d</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_STATE_I2C2            0x4f</span><br><span> #define FCH_AOAC_D3_STATE_I2C3          0x51</span><br><span> #define FCH_AOAC_D3_STATE_UART0         0x57</span><br><span> #define FCH_AOAC_D3_STATE_UART1         0x59</span><br><span> #define FCH_AOAC_D3_STATE_AMBA          0x63</span><br><span> #define FCH_AOAC_D3_STATE_USB2          0x65</span><br><span style="color: hsl(0, 100%, 40%);">-#define FCH_AOAC_D3_STATE_USB3              0x6F</span><br><span style="color: hsl(120, 100%, 40%);">+#define FCH_AOAC_D3_STATE_USB3            0x6f</span><br><span> /* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */</span><br><span> #define   FCH_AOAC_PWR_RST_STATE BIT(0)</span><br><span> #define   FCH_AOAC_RST_CLK_OK_STATE   BIT(1)</span><br><span>@@ -373,20 +373,20 @@</span><br><span> #define   CG1PLL_SPREAD_SPECTRUM_ENABLE               BIT(0)</span><br><span> #define MISC_CGPLL_CONFIG3                    0x10</span><br><span> #define   CG1PLL_REFDIV_SHIFT                   0</span><br><span style="color: hsl(0, 100%, 40%);">-#define   CG1PLL_REFDIV_MASK                   (0x3FF << CG1PLL_REFDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define   CG1PLL_REFDIV_MASK                      (0x3ff << CG1PLL_REFDIV_SHIFT)</span><br><span> #define   CG1PLL_FBDIV_SHIFT                    10</span><br><span style="color: hsl(0, 100%, 40%);">-#define   CG1PLL_FBDIV_MASK                   (0xFFF << CG1PLL_FBDIV_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define   CG1PLL_FBDIV_MASK                        (0xfff << CG1PLL_FBDIV_SHIFT)</span><br><span> #define MISC_CGPLL_CONFIG4                       0x14</span><br><span> #define   CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT      0</span><br><span style="color: hsl(0, 100%, 40%);">-#define   CG1PLL_SS_STEP_SIZE_DSFRAC_MASK      (0xFFFF << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define   CG1PLL_SS_STEP_SIZE_DSFRAC_MASK   (0xffff << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT)</span><br><span> #define   CG1PLL_SS_AMOUNT_DSFRAC_SHIFT           16</span><br><span style="color: hsl(0, 100%, 40%);">-#define   CG1PLL_SS_AMOUNT_DSFRAC_MASK                (0xFFFF << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define   CG1PLL_SS_AMOUNT_DSFRAC_MASK         (0xffff << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT)</span><br><span> #define MISC_CGPLL_CONFIG5                   0x18</span><br><span> #define   CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT     8</span><br><span style="color: hsl(0, 100%, 40%);">-#define   CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK     (0xF << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)</span><br><span style="color: hsl(0, 100%, 40%);">-#define MISC_CGPLL_CONFIG6                      0x1C</span><br><span style="color: hsl(120, 100%, 40%);">+#define   CG1PLL_SS_AMOUNT_NFRAC_SLIP_MASK        (0xf << CG1PLL_SS_AMOUNT_NFRAC_SLIP_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define MISC_CGPLL_CONFIG6                    0x1c</span><br><span> #define   CG1PLL_LF_MODE_SHIFT                  9</span><br><span style="color: hsl(0, 100%, 40%);">-#define   CG1PLL_LF_MODE_MASK                  (0x1FF << CG1PLL_LF_MODE_SHIFT)</span><br><span style="color: hsl(120, 100%, 40%);">+#define   CG1PLL_LF_MODE_MASK                    (0x1ff << CG1PLL_LF_MODE_SHIFT)</span><br><span> #define MISC_CLK_CNTL1                         0x40</span><br><span> #define   CG1PLL_FBDIV_TEST                     BIT(26)</span><br><span> </span><br><span>diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>index 763ddd7..7f0318a 100644</span><br><span>--- a/src/soc/amd/stoneyridge/southbridge.c</span><br><span>+++ b/src/soc/amd/stoneyridge/southbridge.c</span><br><span>@@ -578,14 +578,14 @@</span><br><span> </span><br><span>     uint32_t cfg6 = misc_read32(MISC_CGPLL_CONFIG6);</span><br><span>     cfg6 &= ~CG1PLL_LF_MODE_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">-       cfg6 |= (0x0F8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+      cfg6 |= (0x0f8 << CG1PLL_LF_MODE_SHIFT) & CG1PLL_LF_MODE_MASK;</span><br><span>     misc_write32(MISC_CGPLL_CONFIG6, cfg6);</span><br><span> </span><br><span>  uint32_t cfg3 = misc_read32(MISC_CGPLL_CONFIG3);</span><br><span>     cfg3 &= ~CG1PLL_REFDIV_MASK;</span><br><span>     cfg3 |= (0x003 << CG1PLL_REFDIV_SHIFT) & CG1PLL_REFDIV_MASK;</span><br><span>       cfg3 &= ~CG1PLL_FBDIV_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">- cfg3 |= (0x04B << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+  cfg3 |= (0x04b << CG1PLL_FBDIV_SHIFT) & CG1PLL_FBDIV_MASK;</span><br><span>         misc_write32(MISC_CGPLL_CONFIG3, cfg3);</span><br><span> </span><br><span>  uint32_t cfg5 = misc_read32(MISC_CGPLL_CONFIG5);</span><br><span>@@ -595,9 +595,9 @@</span><br><span> </span><br><span>   uint32_t cfg4 = misc_read32(MISC_CGPLL_CONFIG4);</span><br><span>     cfg4 &= ~CG1PLL_SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">-      cfg4 |= (0xD000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+   cfg4 |= (0xd000 << CG1PLL_SS_AMOUNT_DSFRAC_SHIFT) & CG1PLL_SS_AMOUNT_DSFRAC_MASK;</span><br><span>  cfg4 &= ~CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;</span><br><span style="color: hsl(0, 100%, 40%);">-   cfg4 |= (0x02D5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;</span><br><span style="color: hsl(120, 100%, 40%);">+     cfg4 |= (0x02d5 << CG1PLL_SS_STEP_SIZE_DSFRAC_SHIFT) & CG1PLL_SS_STEP_SIZE_DSFRAC_MASK;</span><br><span>    misc_write32(MISC_CGPLL_CONFIG4, cfg4);</span><br><span> </span><br><span>  rstcfg |= TOGGLE_ALL_PWR_GOOD;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29009">change 29009</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29009"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e </div>
<div style="display:none"> Gerrit-Change-Number: 29009 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Richard Spiegel <richard.spiegel@silverbackltd.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>