[coreboot-gerrit] Change in coreboot[master]: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Tue Oct 2 17:20:31 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28876
Change subject: src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
......................................................................
src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
8 is highest level, so "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8"
will never happen
Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/mainboard/apple/macbook21/romstage.c
M src/mainboard/asus/p5gc-mx/romstage.c
M src/mainboard/getac/p470/romstage.c
M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/kontron/986lcd-m/romstage.c
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/x60/romstage.c
M src/mainboard/lenovo/z61t/romstage.c
M src/mainboard/roda/rk886ex/romstage.c
11 files changed, 11 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28876/1
diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c
index ee322ae..769dcb8 100644
--- a/src/mainboard/apple/macbook21/romstage.c
+++ b/src/mainboard/apple/macbook21/romstage.c
@@ -269,7 +269,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index dacc396..ebace70 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -231,7 +231,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 7498247..5803347 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -281,7 +281,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
index 49a25af..1777ed3 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -185,7 +185,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index 78ec5ed..b49aa82 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -235,7 +235,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 57f32c2..0b67a0c 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -162,7 +162,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 467606a..f29ee43 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -331,7 +331,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c
index e4a8efb..50b8840 100644
--- a/src/mainboard/lenovo/t60/romstage.c
+++ b/src/mainboard/lenovo/t60/romstage.c
@@ -219,7 +219,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 81ee5da..c5a9198 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -221,7 +221,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c
index 94c8a8f..97a9d76 100644
--- a/src/mainboard/lenovo/z61t/romstage.c
+++ b/src/mainboard/lenovo/z61t/romstage.c
@@ -219,7 +219,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index 7f233e8..4279334 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -254,7 +254,7 @@
/* Enable SPD ROMs and DDR-II DRAM */
enable_smbus();
-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))
dump_spd_registers();
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149
Gerrit-Change-Number: 28876
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
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