<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/28876">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/mb: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement<br><br>8 is highest level, so "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8"<br>will never happen<br><br>Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/mainboard/apple/macbook21/romstage.c<br>M src/mainboard/asus/p5gc-mx/romstage.c<br>M src/mainboard/getac/p470/romstage.c<br>M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c<br>M src/mainboard/ibase/mb899/romstage.c<br>M src/mainboard/intel/d945gclf/romstage.c<br>M src/mainboard/kontron/986lcd-m/romstage.c<br>M src/mainboard/lenovo/t60/romstage.c<br>M src/mainboard/lenovo/x60/romstage.c<br>M src/mainboard/lenovo/z61t/romstage.c<br>M src/mainboard/roda/rk886ex/romstage.c<br>11 files changed, 11 insertions(+), 11 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28876/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c</span><br><span>index ee322ae..769dcb8 100644</span><br><span>--- a/src/mainboard/apple/macbook21/romstage.c</span><br><span>+++ b/src/mainboard/apple/macbook21/romstage.c</span><br><span>@@ -269,7 +269,7 @@</span><br><span>     /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>index dacc396..ebace70 100644</span><br><span>--- a/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>+++ b/src/mainboard/asus/p5gc-mx/romstage.c</span><br><span>@@ -231,7 +231,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c</span><br><span>index 7498247..5803347 100644</span><br><span>--- a/src/mainboard/getac/p470/romstage.c</span><br><span>+++ b/src/mainboard/getac/p470/romstage.c</span><br><span>@@ -281,7 +281,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>index 49a25af..1777ed3 100644</span><br><span>--- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c</span><br><span>@@ -185,7 +185,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c</span><br><span>index 78ec5ed..b49aa82 100644</span><br><span>--- a/src/mainboard/ibase/mb899/romstage.c</span><br><span>+++ b/src/mainboard/ibase/mb899/romstage.c</span><br><span>@@ -235,7 +235,7 @@</span><br><span>       /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>index 57f32c2..0b67a0c 100644</span><br><span>--- a/src/mainboard/intel/d945gclf/romstage.c</span><br><span>+++ b/src/mainboard/intel/d945gclf/romstage.c</span><br><span>@@ -162,7 +162,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>index 467606a..f29ee43 100644</span><br><span>--- a/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>+++ b/src/mainboard/kontron/986lcd-m/romstage.c</span><br><span>@@ -331,7 +331,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c</span><br><span>index e4a8efb..50b8840 100644</span><br><span>--- a/src/mainboard/lenovo/t60/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/t60/romstage.c</span><br><span>@@ -219,7 +219,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c</span><br><span>index 81ee5da..c5a9198 100644</span><br><span>--- a/src/mainboard/lenovo/x60/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/x60/romstage.c</span><br><span>@@ -221,7 +221,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c</span><br><span>index 94c8a8f..97a9d76 100644</span><br><span>--- a/src/mainboard/lenovo/z61t/romstage.c</span><br><span>+++ b/src/mainboard/lenovo/z61t/romstage.c</span><br><span>@@ -219,7 +219,7 @@</span><br><span>       /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span>diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c</span><br><span>index 7f233e8..4279334 100644</span><br><span>--- a/src/mainboard/roda/rk886ex/romstage.c</span><br><span>+++ b/src/mainboard/roda/rk886ex/romstage.c</span><br><span>@@ -254,7 +254,7 @@</span><br><span>   /* Enable SPD ROMs and DDR-II DRAM */</span><br><span>        enable_smbus();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8</span><br><span style="color: hsl(120, 100%, 40%);">+if (IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8))</span><br><span>    dump_spd_registers();</span><br><span> #endif</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/28876">change 28876</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/28876"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149 </div>
<div style="display:none"> Gerrit-Change-Number: 28876 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>