[coreboot-gerrit] Change in ...coreboot[master]: soc/fsp_broadwell_de: Add microcode updates pre memory

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29819


Change subject: soc/fsp_broadwell_de: Add microcode updates pre memory
......................................................................

soc/fsp_broadwell_de: Add microcode updates pre memory

Add support for updating microcodes on BDX DE before
memory is initialized without FIT support.

Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
---
M src/drivers/intel/fsp1_0/fsp_util.c
1 file changed, 5 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/29819/1

diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c
index a09b1b1..71f6416 100644
--- a/src/drivers/intel/fsp1_0/fsp_util.c
+++ b/src/drivers/intel/fsp1_0/fsp_util.c
@@ -22,6 +22,7 @@
 #include <lib.h> // hexdump
 #include <ip_checksum.h>
 #include <timestamp.h>
+#include <cpu/intel/microcode.h>
 
 #ifndef __PRE_RAM__
 /* Globals pointers for FSP structures */
@@ -75,6 +76,10 @@
 	UPD_DATA_REGION fsp_upd_data;
 #endif
 
+	/* Load microcode before RAM init */
+	if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
+		intel_update_microcode_from_cbfs();
+
 	memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
 	FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
 	FspInitParams.NvsBufferPtr = NULL;

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770
Gerrit-Change-Number: 29819
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki at gmail.com>
Gerrit-MessageType: newchange
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