<p>Philipp Deppenwiese has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29819">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/fsp_broadwell_de: Add microcode updates pre memory<br><br>Add support for updating microcodes on BDX DE before<br>memory is initialized without FIT support.<br><br>Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770<br>Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com><br>---<br>M src/drivers/intel/fsp1_0/fsp_util.c<br>1 file changed, 5 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/29819/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>index a09b1b1..71f6416 100644</span><br><span>--- a/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>+++ b/src/drivers/intel/fsp1_0/fsp_util.c</span><br><span>@@ -22,6 +22,7 @@</span><br><span> #include <lib.h> // hexdump</span><br><span> #include <ip_checksum.h></span><br><span> #include <timestamp.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <cpu/intel/microcode.h></span><br><span> </span><br><span> #ifndef __PRE_RAM__</span><br><span> /* Globals pointers for FSP structures */</span><br><span>@@ -75,6 +76,10 @@</span><br><span>       UPD_DATA_REGION fsp_upd_data;</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+   /* Load microcode before RAM init */</span><br><span style="color: hsl(120, 100%, 40%);">+  if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))</span><br><span style="color: hsl(120, 100%, 40%);">+             intel_update_microcode_from_cbfs();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>        memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));</span><br><span>     FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;</span><br><span>  FspInitParams.NvsBufferPtr = NULL;</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29819">change 29819</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29819"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: Ie31acaf0fc41c51b9edf65b981d43d7732661770 </div>
<div style="display:none"> Gerrit-Change-Number: 29819 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki@gmail.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>