[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/icelake: Create macros for FSP consumption as per ICL requi...
Shelley Chen (Code Review)
gerrit at coreboot.org
Tue Nov 20 23:41:04 CET 2018
Hello Subrata Banik,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/29748
to review the following change.
Change subject: soc/intel/icelake: Create macros for FSP consumption as per ICL requirement
......................................................................
soc/intel/icelake: Create macros for FSP consumption as per ICL requirement
1. Modify PCIEXBAR to accomodate TCSS RP
2. LPSS device mode selection
3. Add option to emable/disable audio controller.
Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/include/soc/serialio.h
3 files changed, 52 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29748/1
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index c4ee841..727fccee 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -126,6 +126,10 @@
help
This option allows you to select MMIO Base Address of sideband bus.
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xc0000000
+
config CPU_BCLK_MHZ
int
default 100
@@ -146,6 +150,10 @@
int
default 6
+config SOC_INTEL_UART_DEV_MAX
+ int
+ default 3
+
# Clock divider parameters for 115200 baud rate
config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
hex
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index cb06fcb..6bd836e 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -121,6 +121,7 @@
uint8_t SataPortsDevSlp[8];
/* Audio related */
+ uint8_t EnableAzalia;
uint8_t PchHdaEnable;
uint8_t PchHdaDspEnable;
@@ -152,11 +153,16 @@
/* eMMC and SD */
uint8_t ScsEmmcHs400Enabled;
/* Need to update DLL setting to get Emmc running at HS400 speed */
- uint8_t EmmcHs400DllNeed;
- /* 0-39: number of active delay for RX strobe, unit is 125 psec */
- uint8_t EmmcHs400RxStrobeDll1;
- /* 0-78: number of active delay for TX data, unit is 125 psec */
- uint8_t EmmcHs400TxDataDll;
+ uint8_t EmmcUseCustomDlls;
+ uint32_t EmmcTxCmdDelayRegValue;
+ uint32_t EmmcTxDataDelay1RegValue;
+ uint32_t EmmcTxDataDelay2RegValue;
+ uint32_t EmmcRxCmdDataDelay1RegValue;
+ uint32_t EmmcRxCmdDataDelay2RegValue;
+ uint32_t EmmcRxStrobeDelayRegValue;
+
+ /* Enable if SD Card Power Enable Signal is Active High */
+ uint8_t SdCardPowerEnableActiveHigh;
/* Integrated Sensor */
uint8_t PchIshEnable;
@@ -219,28 +225,17 @@
} DebugConsent;
/*
* SerialIO device mode selection:
- *
- * Device index:
- * PchSerialIoIndexI2C0
- * PchSerialIoIndexI2C1
- * PchSerialIoIndexI2C2
- * PchSerialIoIndexI2C3
- * PchSerialIoIndexI2C4
- * PchSerialIoIndexI2C5
- * PchSerialIoIndexSPI0
- * PchSerialIoIndexSPI1
- * PchSerialIoIndexSPI2
- * PchSerialIoIndexUART0
- * PchSerialIoIndexUART1
- * PchSerialIoIndexUART2
- *
- * Mode select:
- * PchSerialIoDisabled
- * PchSerialIoPci
- * PchSerialIoAcpi
- * PchSerialIoHidden
+ * PchSerialIoDisabled,
+ * PchSerialIoPci,
+ * PchSerialIoHidden,
+ * PchSerialIoLegacyUart,
+ * PchSerialIoSkipInit
*/
- uint8_t SerialIoDevMode[PchSerialIoIndexMAX];
+ uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
+ uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
@@ -251,6 +246,14 @@
/* Intel VT configuration */
uint8_t VtdDisable;
uint8_t VmxEnable;
+
+ /* CNVi BT Audio Offload
+ Enable/Disable BT Audio Offload.
+ 0: PLATFORM_POR,
+ 1: FORCE_ENABLE,
+ 2: FORCE_DISABLE.
+ */
+ uint8_t CnviBtAudioOffload;
};
typedef struct soc_intel_icelake_config config_t;
diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h
index 30a48a1..8f18eb8 100644
--- a/src/soc/intel/icelake/include/soc/serialio.h
+++ b/src/soc/intel/icelake/include/soc/serialio.h
@@ -19,9 +19,10 @@
typedef enum {
PchSerialIoDisabled,
PchSerialIoPci,
- PchSerialIoAcpi,
PchSerialIoHidden,
-} PCH_SERIAL_IO_MODE;
+ PchSerialIoLegacyUart,
+ PchSerialIoSkipInit
+ } PCH_SERIAL_IO_MODE;
typedef enum {
PchSerialIoIndexI2C0,
@@ -29,14 +30,19 @@
PchSerialIoIndexI2C2,
PchSerialIoIndexI2C3,
PchSerialIoIndexI2C4,
- PchSerialIoIndexI2C5,
- PchSerialIoIndexSPI0,
- PchSerialIoIndexSPI1,
- PchSerialIoIndexSPI2,
+ PchSerialIoIndexI2C5
+} PCH_SERIAL_IO_I2C_CONTROLLER;
+
+typedef enum {
+ PchSerialIoIndexGSPI0,
+ PchSerialIoIndexGSPI1,
+ PchSerialIoIndexGSPI2
+} PCH_SERIAL_IO_GSPI_CONTROLLER;
+
+typedef enum {
PchSerialIoIndexUART0,
PchSerialIoIndexUART1,
- PchSerialIoIndexUART2,
- PchSerialIoIndexMAX
-} PCH_SERIAL_IO_CONTROLLER;
+ PchSerialIoIndexUART2
+} PCH_SERIAL_IO_UART_CONTROLLER;
#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6
Gerrit-Change-Number: 29748
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-MessageType: newchange
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