<p>Shelley Chen would like Subrata Banik to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/c/coreboot/+/29748">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/icelake: Create macros for FSP consumption as per ICL requirement<br><br>1. Modify PCIEXBAR to accomodate TCSS RP<br>2. LPSS device mode selection<br>3. Add option to emable/disable audio controller.<br><br>Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/icelake/Kconfig<br>M src/soc/intel/icelake/chip.h<br>M src/soc/intel/icelake/include/soc/serialio.h<br>3 files changed, 52 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29748/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig</span><br><span>index c4ee841..727fccee 100644</span><br><span>--- a/src/soc/intel/icelake/Kconfig</span><br><span>+++ b/src/soc/intel/icelake/Kconfig</span><br><span>@@ -126,6 +126,10 @@</span><br><span> help</span><br><span> This option allows you to select MMIO Base Address of sideband bus.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config MMCONF_BASE_ADDRESS</span><br><span style="color: hsl(120, 100%, 40%);">+ hex</span><br><span style="color: hsl(120, 100%, 40%);">+ default 0xc0000000</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> config CPU_BCLK_MHZ</span><br><span> int</span><br><span> default 100</span><br><span>@@ -146,6 +150,10 @@</span><br><span> int</span><br><span> default 6</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+config SOC_INTEL_UART_DEV_MAX</span><br><span style="color: hsl(120, 100%, 40%);">+ int</span><br><span style="color: hsl(120, 100%, 40%);">+ default 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> # Clock divider parameters for 115200 baud rate</span><br><span> config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL</span><br><span> hex</span><br><span>diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h</span><br><span>index cb06fcb..6bd836e 100644</span><br><span>--- a/src/soc/intel/icelake/chip.h</span><br><span>+++ b/src/soc/intel/icelake/chip.h</span><br><span>@@ -121,6 +121,7 @@</span><br><span> uint8_t SataPortsDevSlp[8];</span><br><span> </span><br><span> /* Audio related */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t EnableAzalia;</span><br><span> uint8_t PchHdaEnable;</span><br><span> uint8_t PchHdaDspEnable;</span><br><span> </span><br><span>@@ -152,11 +153,16 @@</span><br><span> /* eMMC and SD */</span><br><span> uint8_t ScsEmmcHs400Enabled;</span><br><span> /* Need to update DLL setting to get Emmc running at HS400 speed */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t EmmcHs400DllNeed;</span><br><span style="color: hsl(0, 100%, 40%);">- /* 0-39: number of active delay for RX strobe, unit is 125 psec */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t EmmcHs400RxStrobeDll1;</span><br><span style="color: hsl(0, 100%, 40%);">- /* 0-78: number of active delay for TX data, unit is 125 psec */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t EmmcHs400TxDataDll;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t EmmcUseCustomDlls;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t EmmcTxCmdDelayRegValue;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t EmmcTxDataDelay1RegValue;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t EmmcTxDataDelay2RegValue;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t EmmcRxCmdDataDelay1RegValue;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t EmmcRxCmdDataDelay2RegValue;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint32_t EmmcRxStrobeDelayRegValue;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Enable if SD Card Power Enable Signal is Active High */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SdCardPowerEnableActiveHigh;</span><br><span> </span><br><span> /* Integrated Sensor */</span><br><span> uint8_t PchIshEnable;</span><br><span>@@ -219,28 +225,17 @@</span><br><span> } DebugConsent;</span><br><span> /*</span><br><span> * SerialIO device mode selection:</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Device index:</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexI2C0</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexI2C1</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexI2C2</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexI2C3</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexI2C4</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexI2C5</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexSPI0</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexSPI1</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexSPI2</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexUART0</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexUART1</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoIndexUART2</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Mode select:</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoDisabled</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoPci</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoAcpi</span><br><span style="color: hsl(0, 100%, 40%);">- * PchSerialIoHidden</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoDisabled,</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoPci,</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoHidden,</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoLegacyUart,</span><br><span style="color: hsl(120, 100%, 40%);">+ * PchSerialIoSkipInit</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t SerialIoDevMode[PchSerialIoIndexMAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX];</span><br><span> </span><br><span> /* GPIO SD card detect pin */</span><br><span> unsigned int sdcard_cd_gpio;</span><br><span>@@ -251,6 +246,14 @@</span><br><span> /* Intel VT configuration */</span><br><span> uint8_t VtdDisable;</span><br><span> uint8_t VmxEnable;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* CNVi BT Audio Offload</span><br><span style="color: hsl(120, 100%, 40%);">+ Enable/Disable BT Audio Offload.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: PLATFORM_POR,</span><br><span style="color: hsl(120, 100%, 40%);">+ 1: FORCE_ENABLE,</span><br><span style="color: hsl(120, 100%, 40%);">+ 2: FORCE_DISABLE.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t CnviBtAudioOffload;</span><br><span> };</span><br><span> </span><br><span> typedef struct soc_intel_icelake_config config_t;</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/serialio.h b/src/soc/intel/icelake/include/soc/serialio.h</span><br><span>index 30a48a1..8f18eb8 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/serialio.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/serialio.h</span><br><span>@@ -19,9 +19,10 @@</span><br><span> typedef enum {</span><br><span> PchSerialIoDisabled,</span><br><span> PchSerialIoPci,</span><br><span style="color: hsl(0, 100%, 40%);">- PchSerialIoAcpi,</span><br><span> PchSerialIoHidden,</span><br><span style="color: hsl(0, 100%, 40%);">-} PCH_SERIAL_IO_MODE;</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoLegacyUart,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoSkipInit</span><br><span style="color: hsl(120, 100%, 40%);">+ } PCH_SERIAL_IO_MODE;</span><br><span> </span><br><span> typedef enum {</span><br><span> PchSerialIoIndexI2C0,</span><br><span>@@ -29,14 +30,19 @@</span><br><span> PchSerialIoIndexI2C2,</span><br><span> PchSerialIoIndexI2C3,</span><br><span> PchSerialIoIndexI2C4,</span><br><span style="color: hsl(0, 100%, 40%);">- PchSerialIoIndexI2C5,</span><br><span style="color: hsl(0, 100%, 40%);">- PchSerialIoIndexSPI0,</span><br><span style="color: hsl(0, 100%, 40%);">- PchSerialIoIndexSPI1,</span><br><span style="color: hsl(0, 100%, 40%);">- PchSerialIoIndexSPI2,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexI2C5</span><br><span style="color: hsl(120, 100%, 40%);">+} PCH_SERIAL_IO_I2C_CONTROLLER;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef enum {</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexGSPI0,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexGSPI1,</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexGSPI2</span><br><span style="color: hsl(120, 100%, 40%);">+} PCH_SERIAL_IO_GSPI_CONTROLLER;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+typedef enum {</span><br><span> PchSerialIoIndexUART0,</span><br><span> PchSerialIoIndexUART1,</span><br><span style="color: hsl(0, 100%, 40%);">- PchSerialIoIndexUART2,</span><br><span style="color: hsl(0, 100%, 40%);">- PchSerialIoIndexMAX</span><br><span style="color: hsl(0, 100%, 40%);">-} PCH_SERIAL_IO_CONTROLLER;</span><br><span style="color: hsl(120, 100%, 40%);">+ PchSerialIoIndexUART2</span><br><span style="color: hsl(120, 100%, 40%);">+} PCH_SERIAL_IO_UART_CONTROLLER;</span><br><span> </span><br><span> #endif</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/c/coreboot/+/29748">change 29748</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/c/coreboot/+/29748"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-Change-Id: I524c7ed116aeb8b353123d7b1d9815b0f249d0e6 </div>
<div style="display:none"> Gerrit-Change-Number: 29748 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Shelley Chen <shchen@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>