[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support

[Frans Hendriks (Code Review)]

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/29662 )

Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
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Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S
File src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S:

https://review.coreboot.org/#/c/29662/5/src/soc/intel/braswell/bootblock/cache_as_ram_cbootblock.S@21
PS5, Line 21: #include <device/pci_def.h>
> that looks like a copy of drivers/intel/fsp1_1/cache_as_ram.inc. […]
Specific support (provide timestamp, bootblock_pre_c_entry label) for C bootblock is required.


https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car_stage.S
File src/soc/intel/braswell/romstage/car_stage.S:

https://review.coreboot.org/#/c/29662/2/src/soc/intel/braswell/romstage/car_stage.S@23
PS2, Line 23: 
> What I meant is 2. Replace all occurence of romstage_c_entry on braswell with car_stage_c_entry. […]
Replacing with car_stage_c_entry() results into a build error on the Intel Quark platforms which have this function in SoC and uses FSP1.1



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Gerrit-Change-Number: 29662
Gerrit-PatchSet: 5
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks at eltan.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Patrick Rudolph <siro at das-labor.org>
Gerrit-Comment-Date: Mon, 19 Nov 2018 14:38:21 +0000
Gerrit-HasComments: Yes
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