[coreboot-gerrit] Change in coreboot[master]: soc/intel/icelake: Make correct IRQ mapping for ICL SA and PCH PCI de...
Subrata Banik (Code Review)
gerrit at coreboot.org
Tue Nov 6 12:42:51 CET 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/29508
Change subject: soc/intel/icelake: Make correct IRQ mapping for ICL SA and PCH PCI devices
......................................................................
soc/intel/icelake: Make correct IRQ mapping for ICL SA and PCH PCI devices
This patch provides option for PCI IRQ mapping in both PIC and APIC mode
based on ICL RC code.
Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/icelake/acpi/pci_irqs.asl
M src/soc/intel/icelake/include/soc/irq.h
2 files changed, 39 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29508/1
diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl
index d346ce2..346138b 100644
--- a/src/soc/intel/icelake/acpi/pci_irqs.asl
+++ b/src/soc/intel/icelake/acpi/pci_irqs.asl
@@ -57,10 +57,10 @@
Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
- /* D20: xHCI, OTG, SRAM, CNVi WiFi */
+ /* D20: xHCI, SRAM, OTG, CNVi WiFi */
Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
- Package(){0x0014FFFF, 1, 0, OTG_IRQ },
- Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
+ Package(){0x0014FFFF, 1, 0, PMC_SRAM_IRQ },
+ Package(){0x0014FFFF, 2, 0, OTG_IRQ },
Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
/* Integrated Sensor Hub */
Package(){0x0013FFFF, 0, 0, ISH_IRQ },
@@ -84,51 +84,49 @@
Name (PICN, Package () {
/* D31: cAVS, SMBus, GbE, Nothpeak */
- Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
- Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
- Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
- Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
+ Package () { 0x001FFFFF, 0, 0, 11 },
+ Package () { 0x001FFFFF, 1, 0, 10 },
+ Package () { 0x001FFFFF, 2, 0, 11 },
+ Package () { 0x001FFFFF, 3, 0, 11 },
/* D32: Can't use PIC*/
/* D29: PCI Express Port 9-16 */
- Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
- Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
- Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
- Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
+ Package () { 0x001DFFFF, 0, 0, 11 },
+ Package () { 0x001DFFFF, 1, 0, 10 },
+ Package () { 0x001DFFFF, 2, 0, 11 },
+ Package () { 0x001DFFFF, 3, 0, 11 },
/* D28: PCI Express Port 1-8 */
- Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
- Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
- Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
- Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
+ Package () { 0x001CFFFF, 0, 0, 11 },
+ Package () { 0x001CFFFF, 1, 0, 10 },
+ Package () { 0x001CFFFF, 2, 0, 11 },
+ Package () { 0x001CFFFF, 3, 0, 11 },
+ /* D26: Can't use PIC*/
/* D25: Can't use PIC*/
- /* D23 */
- Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ /* D23: SATA controller */
+ Package () { 0x0017FFFF, 0, 0, 11 },
/* D22: CSME (HECI, IDE-R, KT redirection */
- Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
- Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
- Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
- Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
- /* D21: Can't use PIC*/
- /* D20: xHCI, OTG, SRAM, CNVi WiFi */
- Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
- Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
- Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
- Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
- /* D19: Can't use PIC*/
- /* Thermal */
- Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0016FFFF, 0, 0, 11 },
+ Package () { 0x0016FFFF, 1, 0, 10 },
+ Package () { 0x0016FFFF, 2, 0, 11 },
+ Package () { 0x0016FFFF, 3, 0, 11 },
+ /* D20: xHCI, SRAM, OTG, CNVi WiFi */
+ Package () { 0x0014FFFF, 0, 0, 11 },
+ Package () { 0x0014FFFF, 1, 0, 10 },
+ Package () { 0x0014FFFF, 2, 0, 11 },
+ Package () { 0x0014FFFF, 3, 0, 11 },
+ /* D18: Can't use PIC*/
/* P.E.G. Root Port D1F0 */
- Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
- Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
- Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
- Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
+ Package () { 0x0001FFFF, 0, 0, 11 },
+ Package () { 0x0001FFFF, 1, 0, 10 },
+ Package () { 0x0001FFFF, 2, 0, 11 },
+ Package () { 0x0001FFFF, 3, 0, 11 },
/* SA IGFX Device */
- Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0002FFFF, 0, 0, 11 },
/* SA Thermal Device */
- Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0004FFFF, 0, 0, 11 },
/* SA IPU Device */
- Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0005FFFF, 0, 0, 11 },
/* SA GNA Device */
- Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
+ Package () { 0x0008FFFF, 0, 0, 11 },
})
Method (_PRT)
diff --git a/src/soc/intel/icelake/include/soc/irq.h b/src/soc/intel/icelake/include/soc/irq.h
index 2f980ff..1d17c4a 100644
--- a/src/soc/intel/icelake/include/soc/irq.h
+++ b/src/soc/intel/icelake/include/soc/irq.h
@@ -85,10 +85,10 @@
#define HECI_3_IRQ 16
#define XHCI_IRQ 16
-#define OTG_IRQ 17
-#define PMC_SRAM_IRQ 18
-#define THERMAL_IRQ 16
+#define PMC_SRAM_IRQ 17
+#define OTG_IRQ 18
#define CNViWIFI_IRQ 19
+#define THERMAL_IRQ 16
#define UFS_IRQ 16
#define CIO_INTA_IRQ 16
#define CIO_INTD_IRQ 19
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9
Gerrit-Change-Number: 29508
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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