<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29508">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/icelake: Make correct IRQ mapping for ICL SA and PCH PCI devices<br><br>This patch provides option for PCI IRQ mapping in both PIC and APIC mode<br>based on ICL RC code.<br><br>Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/icelake/acpi/pci_irqs.asl<br>M src/soc/intel/icelake/include/soc/irq.h<br>2 files changed, 39 insertions(+), 41 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/29508/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/icelake/acpi/pci_irqs.asl b/src/soc/intel/icelake/acpi/pci_irqs.asl</span><br><span>index d346ce2..346138b 100644</span><br><span>--- a/src/soc/intel/icelake/acpi/pci_irqs.asl</span><br><span>+++ b/src/soc/intel/icelake/acpi/pci_irqs.asl</span><br><span>@@ -57,10 +57,10 @@</span><br><span> Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },</span><br><span> Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },</span><br><span> Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },</span><br><span style="color: hsl(0, 100%, 40%);">- /* D20: xHCI, OTG, SRAM, CNVi WiFi */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20: xHCI, SRAM, OTG, CNVi WiFi */</span><br><span> Package(){0x0014FFFF, 0, 0, XHCI_IRQ },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0014FFFF, 1, 0, OTG_IRQ },</span><br><span style="color: hsl(0, 100%, 40%);">- Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 1, 0, PMC_SRAM_IRQ },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package(){0x0014FFFF, 2, 0, OTG_IRQ },</span><br><span> Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },</span><br><span> /* Integrated Sensor Hub */</span><br><span> Package(){0x0013FFFF, 0, 0, ISH_IRQ },</span><br><span>@@ -84,51 +84,49 @@</span><br><span> </span><br><span> Name (PICN, Package () {</span><br><span> /* D31: cAVS, SMBus, GbE, Nothpeak */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 0, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 1, 0, 10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 2, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001FFFFF, 3, 0, 11 },</span><br><span> /* D32: Can't use PIC*/</span><br><span> /* D29: PCI Express Port 9-16 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 0, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 1, 0, 10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 2, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001DFFFF, 3, 0, 11 },</span><br><span> /* D28: PCI Express Port 1-8 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 0, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 1, 0, 10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 2, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x001CFFFF, 3, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D26: Can't use PIC*/</span><br><span> /* D25: Can't use PIC*/</span><br><span style="color: hsl(0, 100%, 40%);">- /* D23 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D23: SATA controller */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0017FFFF, 0, 0, 11 },</span><br><span> /* D22: CSME (HECI, IDE-R, KT redirection */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- /* D21: Can't use PIC*/</span><br><span style="color: hsl(0, 100%, 40%);">- /* D20: xHCI, OTG, SRAM, CNVi WiFi */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- /* D19: Can't use PIC*/</span><br><span style="color: hsl(0, 100%, 40%);">- /* Thermal */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 0, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 1, 0, 10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 2, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0016FFFF, 3, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D20: xHCI, SRAM, OTG, CNVi WiFi */</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 0, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 1, 0, 10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 2, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0014FFFF, 3, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ /* D18: Can't use PIC*/</span><br><span> /* P.E.G. Root Port D1F0 */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 0, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 1, 0, 10 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 2, 0, 11 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0001FFFF, 3, 0, 11 },</span><br><span> /* SA IGFX Device */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0002FFFF, 0, 0, 11 },</span><br><span> /* SA Thermal Device */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0004FFFF, 0, 0, 11 },</span><br><span> /* SA IPU Device */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0005FFFF, 0, 0, 11 },</span><br><span> /* SA GNA Device */</span><br><span style="color: hsl(0, 100%, 40%);">- Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ Package () { 0x0008FFFF, 0, 0, 11 },</span><br><span> })</span><br><span> </span><br><span> Method (_PRT)</span><br><span>diff --git a/src/soc/intel/icelake/include/soc/irq.h b/src/soc/intel/icelake/include/soc/irq.h</span><br><span>index 2f980ff..1d17c4a 100644</span><br><span>--- a/src/soc/intel/icelake/include/soc/irq.h</span><br><span>+++ b/src/soc/intel/icelake/include/soc/irq.h</span><br><span>@@ -85,10 +85,10 @@</span><br><span> #define HECI_3_IRQ 16</span><br><span> </span><br><span> #define XHCI_IRQ 16</span><br><span style="color: hsl(0, 100%, 40%);">-#define OTG_IRQ 17</span><br><span style="color: hsl(0, 100%, 40%);">-#define PMC_SRAM_IRQ 18</span><br><span style="color: hsl(0, 100%, 40%);">-#define THERMAL_IRQ 16</span><br><span style="color: hsl(120, 100%, 40%);">+#define PMC_SRAM_IRQ 17</span><br><span style="color: hsl(120, 100%, 40%);">+#define OTG_IRQ 18</span><br><span> #define CNViWIFI_IRQ 19</span><br><span style="color: hsl(120, 100%, 40%);">+#define THERMAL_IRQ 16</span><br><span> #define UFS_IRQ 16</span><br><span> #define CIO_INTA_IRQ 16</span><br><span> #define CIO_INTD_IRQ 19</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29508">change 29508</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29508"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9 </div>
<div style="display:none"> Gerrit-Change-Number: 29508 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>