[coreboot-gerrit] Change in coreboot[master]: vendorcode/intel/fsp/fsp2.0/glk: Add PmicPmcIpcCtrl

[John Zhao (Code Review)]

John Zhao has uploaded this change for review. ( https://review.coreboot.org/29482


Change subject: vendorcode/intel/fsp/fsp2.0/glk: Add PmicPmcIpcCtrl
......................................................................

vendorcode/intel/fsp/fsp2.0/glk: Add PmicPmcIpcCtrl

FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK to improve cold boot
and S3 resume performance.

BUG=b:118676361
TEST=None
Change-Id: I8dc38d2a2a33829efb0083de91a367e048188ee9
Signed-off-by: John Zhao <john.zhao at intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
1 file changed, 8 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29482/1

diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
index cc194b2..18a43e2 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -1715,9 +1715,15 @@
 **/
   UINT8                       SkipSpiPCP;
 
-/** Offset 0x03AB
+/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration
+  Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset
+  (23:16) + OR Value (15:8) + AND Value (7:0)
 **/
-  UINT8                       ReservedFspsUpd[5];
+  UINT32                      PmicPmcIpcCtrl;
+
+/** Offset 0x03AF
+**/
+  UINT8                       ReservedFspsUpd[1];
 } FSP_S_CONFIG;
 
 /** Fsp S SGX Configuration

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8dc38d2a2a33829efb0083de91a367e048188ee9
Gerrit-Change-Number: 29482
Gerrit-PatchSet: 1
Gerrit-Owner: John Zhao <john.zhao at intel.com>
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