<p>John Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/29482">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vendorcode/intel/fsp/fsp2.0/glk: Add PmicPmcIpcCtrl<br><br>FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure<br>PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK to improve cold boot<br>and S3 resume performance.<br><br>BUG=b:118676361<br>TEST=None<br>Change-Id: I8dc38d2a2a33829efb0083de91a367e048188ee9<br>Signed-off-by: John Zhao <john.zhao@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h<br>1 file changed, 8 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29482/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>index cc194b2..18a43e2 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h</span><br><span>@@ -1715,9 +1715,15 @@</span><br><span> **/</span><br><span>   UINT8                       SkipSpiPCP;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x03AB</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+  Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset</span><br><span style="color: hsl(120, 100%, 40%);">+  (23:16) + OR Value (15:8) + AND Value (7:0)</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">-  UINT8                       ReservedFspsUpd[5];</span><br><span style="color: hsl(120, 100%, 40%);">+  UINT32                      PmicPmcIpcCtrl;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x03AF</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+  UINT8                       ReservedFspsUpd[1];</span><br><span> } FSP_S_CONFIG;</span><br><span> </span><br><span> /** Fsp S SGX Configuration</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/29482">change 29482</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/29482"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8dc38d2a2a33829efb0083de91a367e048188ee9 </div>
<div style="display:none"> Gerrit-Change-Number: 29482 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John Zhao <john.zhao@intel.com> </div>