[coreboot-gerrit] Change in coreboot[master]: mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode
Aamir Bohra (Code Review)
gerrit at coreboot.org
Thu May 31 12:25:20 CEST 2018
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/26731
Change subject: mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode
......................................................................
mb/*/*: Update IOAPIC GPIO pad configuration to include trigger mode
Update GPIO pad configuartion in IOAPIC invert mode to include
RX level/edge Configuration.
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85dab
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/mainboard/google/octopus/variants/baseboard/gpio.c
M src/mainboard/google/octopus/variants/bip/gpio.c
M src/mainboard/google/reef/variants/baseboard/gpio.c
M src/mainboard/google/reef/variants/coral/gpio.c
M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
6 files changed, 27 insertions(+), 27 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/26731/1
diff --git a/src/mainboard/google/octopus/variants/baseboard/gpio.c b/src/mainboard/google/octopus/variants/baseboard/gpio.c
index f839850..bf9bd7b 100644
--- a/src/mainboard/google/octopus/variants/baseboard/gpio.c
+++ b/src/mainboard/google/octopus/variants/baseboard/gpio.c
@@ -193,7 +193,7 @@
// TODO Need to set HIZCRx1
PAD_CFG_GPI(GPIO_134, NONE, DEEP),/* GPIO_134 -- SD_CD_OD */
- PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP, LEVEL),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */
PAD_CFG_GPI(GPIO_138, NONE, DEEP),/* GPIO_138 -- PEN_PDCT_ODL */
diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c
index 17fc105..231f942 100644
--- a/src/mainboard/google/octopus/variants/bip/gpio.c
+++ b/src/mainboard/google/octopus/variants/bip/gpio.c
@@ -191,7 +191,7 @@
// TODO Need to set HIZCRx1
PAD_CFG_GPI(GPIO_134, NONE, DEEP),/* GPIO_134 -- SD_CD_OD */
- PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_135, NONE, DEEP, LEVEL),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */
PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */
PAD_CFG_GPI(GPIO_138, NONE, DEEP),/* GPIO_138 -- PEN_PDCT_ODL */
diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c
index 3cd765b..110f257 100644
--- a/src/mainboard/google/reef/variants/baseboard/gpio.c
+++ b/src/mainboard/google/reef/variants/baseboard/gpio.c
@@ -263,7 +263,7 @@
PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */
PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */
/* Headset interrupt */
- PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */
+ PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP, LEVEL), /* SIO_SPI_1_RXD */
PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */
/* SIO_SPI_2 -- unused */
@@ -286,31 +286,31 @@
PAD_CFG_GPI(GPIO_7, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_8, UP_20K, DEEP),
- PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP, LEVEL), /* dTPM IRQ */
PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */
PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP), /* PEN_INT_ODL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP, LEVEL), /* PEN_INT_ODL */
PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */
PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */
PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* 1 vs 4 DMIC config */
- PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP, LEVEL), /* Trackpad IRQ */
PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */
- PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP, LEVEL), /* NFC IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP, LEVEL), /* Touch IRQ */
PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE), /* EC wake */
PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_24, NONE, DEEP), /* PEN_PDCT_ODL */
PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */
PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */
- PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP, LEVEL), /* KB IRQ */
PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */
PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */
- PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP, LEVEL), /* PMIC IRQ */
PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */
PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */
PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */
@@ -358,7 +358,7 @@
/* I2C2 - TPM */
PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
- PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */
/* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */
};
@@ -373,7 +373,7 @@
/* GPIO settings before entering sleep. */
static const struct pad_config sleep_gpio_table[] = {
PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
- PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */
};
const struct pad_config * __weak
diff --git a/src/mainboard/google/reef/variants/coral/gpio.c b/src/mainboard/google/reef/variants/coral/gpio.c
index e89e5b5..f97b66a 100644
--- a/src/mainboard/google/reef/variants/coral/gpio.c
+++ b/src/mainboard/google/reef/variants/coral/gpio.c
@@ -263,7 +263,7 @@
PAD_CFG_GPI(GPIO_112, UP_20K, DEEP), /* SIO_SPI_1_FS0 */
PAD_CFG_GPI(GPIO_113, UP_20K, DEEP), /* SIO_SPI_1_FS1 */
/* Headset interrupt */
- PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP), /* SIO_SPI_1_RXD */
+ PAD_CFG_GPI_APIC_LOW(GPIO_116, NONE, DEEP, LEVEL), /* SIO_SPI_1_RXD */
PAD_CFG_GPI(GPIO_117, UP_20K, DEEP), /* SIO_SPI_1_TXD */
/* SIO_SPI_2 -- unused */
@@ -286,31 +286,31 @@
PAD_CFG_GPI(GPIO_7, UP_20K, DEEP),
PAD_CFG_GPI(GPIO_8, UP_20K, DEEP),
- PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP), /* dTPM IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_9, NONE, DEEP, LEVEL), /* dTPM IRQ */
PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* Board phase enforcement */
PAD_CFG_GPI_SCI_LOW(GPIO_11, NONE, DEEP, EDGE_SINGLE), /* EC SCI */
PAD_CFG_GPI(GPIO_12, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP), /* PEN_INT_ODL */
+ PAD_CFG_GPI_APIC_LOW(GPIO_13, NONE, DEEP, LEVEL), /* PEN_INT_ODL */
PAD_CFG_GPI_APIC_HIGH(GPIO_14, DN_20K, DEEP), /* FP_INT */
PAD_CFG_GPI_SCI_LOW(GPIO_15, NONE, DEEP, EDGE_SINGLE), /* TRACKPAD_INT_1V8_ODL */
PAD_CFG_GPI(GPIO_16, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* 1 vs 4 DMIC config */
- PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP), /* Trackpad IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_18, NONE, DEEP, LEVEL), /* Trackpad IRQ */
PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP), /* NFC IRQ */
- PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP), /* Touch IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, UP_20K, DEEP, LEVEL), /* NFC IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_21, NONE, DEEP, LEVEL), /* Touch IRQ */
PAD_CFG_GPI_SCI_LOW(GPIO_22, NONE, DEEP, EDGE_SINGLE), /* EC wake */
PAD_CFG_GPI(GPIO_23, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_24, NONE, DEEP), /* PEN_PDCT_ODL */
PAD_CFG_GPI(GPIO_25, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_26, UP_20K, DEEP), /* unused */
PAD_CFG_GPI(GPIO_27, UP_20K, DEEP), /* unused */
- PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */
PAD_CFG_GPO(GPIO_29, 1, DEEP), /* FP reset */
- PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP), /* KB IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_30, NONE, DEEP, LEVEL), /* KB IRQ */
PAD_CFG_GPO(GPIO_31, 0, DEEP), /* NFC FW DL */
PAD_CFG_NF(GPIO_32, NONE, DEEP, NF5), /* SUS_CLK2 */
- PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP), /* PMIC IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_33, NONE, DEEP, LEVEL), /* PMIC IRQ */
PAD_CFG_GPI(GPIO_34, UP_20K, DEEP), /* unused */
PAD_CFG_GPO(GPIO_35, 0, DEEP), /* PEN_RESET - active high */
PAD_CFG_GPO(GPIO_36, 0, DEEP), /* touch reset */
@@ -358,7 +358,7 @@
/* I2C2 - TPM */
PAD_CFG_NF(GPIO_128, UP_2K, DEEP, NF1), /* LPSS_I2C2_SDA */
PAD_CFG_NF(GPIO_129, UP_2K, DEEP, NF1), /* LPSS_I2C2_SCL */
- PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP), /* TPM IRQ */
+ PAD_CFG_GPI_APIC_LOW(GPIO_28, NONE, DEEP, LEVEL), /* TPM IRQ */
/* WLAN_PE_RST - default to deasserted just in case FSP misbehaves. */
PAD_CFG_GPO(GPIO_122, 0, DEEP), /* SIO_SPI_2_RXD */
};
@@ -372,14 +372,14 @@
/* Default GPIO settings before entering sleep. */
static const struct pad_config default_sleep_gpio_table[] = {
PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
- PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */
};
/* GPIO settings before entering S5, which are same as default_sleep_gpio_table
* but also turn off EN_PP3300_DX_LTE_SOC. */
static const struct pad_config s5_sleep_gpio_table[] = {
PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
- PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */
PAD_CFG_GPO(GPIO_78, 0, DEEP), /* I2S1_SDO -- EN_PP3300_DX_LTE_SOC */
};
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
index fa9d0e9..955126a 100644
--- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c
@@ -50,7 +50,7 @@
/* A19 : ISH_GP_1 */
PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),
/* A20 : aduio codec irq */
- PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),
+ PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP, LEVEL),
/* A21 : ISH_GP_3 */
PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),
/* A22 : ISH_GP_4 */
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
index 7ff68a4..c763eca 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c
@@ -274,7 +274,7 @@
static const struct pad_config sleep_gpio_table[] = {
#if 0
PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */
- PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */
+ PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP, LEVEL), /* NFC_INT_L */
#endif
};
--
To view, visit https://review.coreboot.org/26731
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85dab
Gerrit-Change-Number: 26731
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180531/2a666590/attachment-0001.html>
More information about the coreboot-gerrit
mailing list