[coreboot-gerrit] Change in coreboot[master]: [WIP]KBL: Update FSP headers - upgrade to FSP 3.3.0
Balaji Manigandan (Code Review)
gerrit at coreboot.org
Tue May 29 14:20:37 CEST 2018
Balaji Manigandan has uploaded this change for review. ( https://review.coreboot.org/26665
Change subject: [WIP]KBL: Update FSP headers - upgrade to FSP 3.3.0
......................................................................
[WIP]KBL: Update FSP headers - upgrade to FSP 3.3.0
FSP update to version 3.3.0
CQ-DEPEND=CL:*632154,CL:*632155,CL:632156
BUG=None
BRANCH=None
TEST=Build and test on Soraka
Change-Id: I7db337bee80cb6a34d0f65d2cd7b9541c7aead94
Signed-off-by: Balaji Manigandan B <balaji.manigandan at intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
M src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
5 files changed, 132 insertions(+), 83 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/26665/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
index c8cdc5f..5a32d78 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
@@ -1,20 +1,34 @@
/** @file
FSP CPU Data Config Block.
- at copyright
- Copyright (c) 2016 Intel Corporation. All rights reserved
- This software and associated documentation (if any) is furnished
- under a license and may only be used or copied in accordance
- with the terms of the license. Except as permitted by the
- license, no part of this software or documentation may be
- reproduced, stored in a retrieval system, or transmitted in any
- form or by any means without the express written consent of
- Intel Corporation.
- This file contains an 'Intel Peripheral Driver' and is uniquely
- identified as "Intel Reference Module" and is licensed for Intel
- CPUs and chipsets under the terms of your license agreement with
- Intel or your vendor. This file may be modified by the user, subject
- to additional terms of the license agreement.
+ @copyright
+ INTEL CONFIDENTIAL
+ Copyright 2016 Intel Corporation.
+
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
+
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
+
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
+
+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+ the terms of your license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the license agreement.
@par Specification Reference:
**/
@@ -63,9 +77,10 @@
UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
UINT32 RsvdBits : 15; ///< Reserved for future use
UINT32 Reserved;
- } Bits;
- UINT32 Uint32[2];
-} CPU_CONFIG_FSP_DATA;
+ } Bits;
+ UINT32 Uint32[2];
+ } CPU_CONFIG_FSP_DATA;
+
#pragma pack (pop)
#endif // _CPU_CONFIG_FSP_DATA_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
index bea3509..9fe4972 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
@@ -1,6 +1,7 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ @copyright
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
index 5d9e0c2..e7c6839 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
@@ -1,6 +1,7 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ @copyright
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -741,7 +742,7 @@
/** Offset 0x02CF - Maximum Core Turbo Ratio Override
Maximum core turbo ratio override allows to increase CPU core frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
**/
UINT8 CoreMaxOcRatio;
@@ -752,13 +753,13 @@
UINT8 CoreVoltageMode;
/** Offset 0x02D1 - Minimum clr turbo ratio override
- Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83
+ Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-255
**/
UINT8 RingMinOcRatio;
/** Offset 0x02D2 - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
**/
UINT8 RingMaxOcRatio;
@@ -905,11 +906,26 @@
**/
UINT8 FlashWearOutProtection;
-/** Offset 0x0301 - ReservedSecurityPreMem
+/** Offset 0x0301 - Thermal Velocity Boost Ratio clipping
+ 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
+ caused by high package temperatures for processors that implement the Intel Thermal
+ Velocity Boost (TVB) feature
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 TvbRatioClipping;
+
+/** Offset 0x0302 - Thermal Velocity Boost voltage optimization
+ 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
+ for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 TvbVoltageOptimization;
+
+/** Offset 0x0303 - ReservedSecurityPreMem
Reserved for Security Pre-Mem
$EN_DIS
**/
- UINT8 ReservedSecurityPreMem[9];
+ UINT8 ReservedSecurityPreMem[7];
/** Offset 0x030A - PCH HPET Enabled
Enable/disable PCH HPET.
@@ -1261,9 +1277,15 @@
**/
UINT8 CleanMemory;
-/** Offset 0x051C
+/** Offset 0x051C - TjMax Offset
+ TjMax offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support
+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 0 - 63
**/
- UINT8 ReservedFspmUpd[4];
+ UINT8 TjMaxOffset;
+
+/** Offset 0x051D
+**/
+ UINT8 ReservedFspmUpd[3];
} FSP_M_CONFIG;
/** Fsp M Test Configuration
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index 0209245..39a08d7 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -1,6 +1,7 @@
/** @file
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+ @copyright
+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -513,9 +514,8 @@
UINT8 PavpEnable;
/** Offset 0x0216 - CdClock Frequency selection
- 0=308.57 Mhz, 1=337.5 Mhz, 2=432 Mhz, 3=450 Mhz, 4=540 Mhz, 5=617.14 Mhz, 6(Default)= 675 Mhz
- 0: 308.57 Mhz, 1: 337.5 Mhz, 2: 432 Mhz, 3: 450 Mhz, 4: 540 Mhz, 5: 617.14 Mhz,
- 6: 675 Mhz
+ 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz
+ 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
**/
UINT8 CdClock;
@@ -538,7 +538,7 @@
UINT8 GmmEnable;
/** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table
- 0=Disable/Clear, 1(Default)=Enable/Set
+ 0=Disable/Clear, 1=Enable/Set
$EN_DIS
**/
UINT8 X2ApicOptOut;
@@ -670,9 +670,16 @@
**/
UINT16 TdcPowerLimit[5];
-/** Offset 0x0290
+/** Offset 0x0290 - CPU VR Power Delivery Design
+ Used to communicate the power delivery design capability of the board. This value
+ is an enum of the available power delivery segments that are defined in the Platform
+ Design Guide.
**/
- UINT8 UnusedUpdSpace11[8];
+ UINT32 VrPowerDeliveryDesign;
+
+/** Offset 0x0294
+**/
+ UINT8 UnusedUpdSpace11[4];
/** Offset 0x0298 - AcLoadline
PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
@@ -1980,9 +1987,15 @@
**/
UINT8 SataRstOptaneMemory;
-/** Offset 0x0721
+/** Offset 0x0721 - PCH SATA RST CPU attached storage
+ RST CPU attached storage
+ $EN_DIS
**/
- UINT8 UnusedUpdSpace19[3];
+ UINT8 SataRstCpuAttachedStorage;
+
+/** Offset 0x0722
+**/
+ UINT8 UnusedUpdSpace19[2];
/** Offset 0x0724 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -2170,31 +2183,28 @@
UINT8 SaPostMemTestRsvd[11];
/** Offset 0x079C - 1-Core Ratio Limit
- 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
- to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,
- 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83
+ 1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 1-Core
+ Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
+ 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
+ 8-Core Ratio Limit. Range is 0 to 255
**/
UINT8 OneCoreRatioLimit;
/** Offset 0x079D - 2-Core Ratio Limit
- 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
+ 2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 2-Core
+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 TwoCoreRatioLimit;
/** Offset 0x079E - 3-Core Ratio Limit
- 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
+ 3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 3-Core
+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 ThreeCoreRatioLimit;
/** Offset 0x079F - 4-Core Ratio Limit
- 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
+ 4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 4-Core
+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 FourCoreRatioLimit;
@@ -2771,30 +2781,26 @@
UINT32 CpuS3ResumeData;
/** Offset 0x0884 - 5-Core Ratio Limit
- 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
+ 5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 5-Core
+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 FiveCoreRatioLimit;
/** Offset 0x0885 - 6-Core Ratio Limit
- 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
+ 6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 6-Core
+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 SixCoreRatioLimit;
/** Offset 0x0886 - 7-Core Ratio Limit
- 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
+ 7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 7-Core
+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 SevenCoreRatioLimit;
/** Offset 0x0887 - 8-Core Ratio Limit
- 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
+ 8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 8-Core
+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
**/
UINT8 EightCoreRatioLimit;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
index 248b4d5..11f79ca 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
@@ -1,33 +1,38 @@
/** @file
+ This file contains definitions required for creation of
+ Memory S3 Save data, Memory Info data and Memory Platform
+ data hobs.
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+ @copyright
+ INTEL CONFIDENTIAL
+ Copyright 1999 - 2017 Intel Corporation.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
+ The source code contained or described herein and all documents related to the
+ source code ("Material") are owned by Intel Corporation or its suppliers or
+ licensors. Title to the Material remains with Intel Corporation or its suppliers
+ and licensors. The Material may contain trade secrets and proprietary and
+ confidential information of Intel Corporation and its suppliers and licensors,
+ and is protected by worldwide copyright and trade secret laws and treaty
+ provisions. No part of the Material may be used, copied, reproduced, modified,
+ published, uploaded, posted, transmitted, distributed, or disclosed in any way
+ without Intel's prior express written permission.
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
+ No license under any patent, copyright, trade secret or other intellectual
+ property right is granted to or conferred upon you by disclosure or delivery
+ of the Materials, either expressly, by implication, inducement, estoppel or
+ otherwise. Any license under such intellectual property rights must be
+ express and approved by Intel in writing.
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
+ Unless otherwise agreed by Intel in writing, you may not remove or alter
+ this notice or any other notice embedded in Materials by Intel or
+ Intel's suppliers or licensors in any way.
- This file is automatically generated. Please do NOT modify !!!
+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as
+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under
+ the terms of your license agreement with Intel or your vendor. This file may
+ be modified by the user, subject to additional terms of the license agreement.
+ at par Specification Reference:
**/
#ifndef _MEM_INFO_HOB_H_
#define _MEM_INFO_HOB_H_
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7db337bee80cb6a34d0f65d2cd7b9541c7aead94
Gerrit-Change-Number: 26665
Gerrit-PatchSet: 1
Gerrit-Owner: Balaji Manigandan <balaji.manigandan at intel.com>
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