<p>Balaji Manigandan has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26665">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP]KBL: Update FSP headers - upgrade to FSP 3.3.0<br><br>FSP update to version 3.3.0<br><br>CQ-DEPEND=CL:*632154,CL:*632155,CL:632156<br>BUG=None<br>BRANCH=None<br>TEST=Build and test on Soraka<br><br>Change-Id: I7db337bee80cb6a34d0f65d2cd7b9541c7aead94<br>Signed-off-by: Balaji Manigandan B <balaji.manigandan@intel.com><br>---<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h<br>M src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h<br>5 files changed, 132 insertions(+), 83 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/26665/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h</span><br><span>index c8cdc5f..5a32d78 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h</span><br><span>@@ -1,20 +1,34 @@</span><br><span> /** @file</span><br><span> FSP CPU Data Config Block.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-@copyright</span><br><span style="color: hsl(0, 100%, 40%);">- Copyright (c) 2016 Intel Corporation. All rights reserved</span><br><span style="color: hsl(0, 100%, 40%);">- This software and associated documentation (if any) is furnished</span><br><span style="color: hsl(0, 100%, 40%);">- under a license and may only be used or copied in accordance</span><br><span style="color: hsl(0, 100%, 40%);">- with the terms of the license. Except as permitted by the</span><br><span style="color: hsl(0, 100%, 40%);">- license, no part of this software or documentation may be</span><br><span style="color: hsl(0, 100%, 40%);">- reproduced, stored in a retrieval system, or transmitted in any</span><br><span style="color: hsl(0, 100%, 40%);">- form or by any means without the express written consent of</span><br><span style="color: hsl(0, 100%, 40%);">- Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- This file contains an 'Intel Peripheral Driver' and is uniquely</span><br><span style="color: hsl(0, 100%, 40%);">- identified as "Intel Reference Module" and is licensed for Intel</span><br><span style="color: hsl(0, 100%, 40%);">- CPUs and chipsets under the terms of your license agreement with</span><br><span style="color: hsl(0, 100%, 40%);">- Intel or your vendor. This file may be modified by the user, subject</span><br><span style="color: hsl(0, 100%, 40%);">- to additional terms of the license agreement.</span><br><span style="color: hsl(120, 100%, 40%);">+ @copyright</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL CONFIDENTIAL</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright 2016 Intel Corporation.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ The source code contained or described herein and all documents related to the</span><br><span style="color: hsl(120, 100%, 40%);">+ source code ("Material") are owned by Intel Corporation or its suppliers or</span><br><span style="color: hsl(120, 100%, 40%);">+ licensors. Title to the Material remains with Intel Corporation or its suppliers</span><br><span style="color: hsl(120, 100%, 40%);">+ and licensors. The Material may contain trade secrets and proprietary and</span><br><span style="color: hsl(120, 100%, 40%);">+ confidential information of Intel Corporation and its suppliers and licensors,</span><br><span style="color: hsl(120, 100%, 40%);">+ and is protected by worldwide copyright and trade secret laws and treaty</span><br><span style="color: hsl(120, 100%, 40%);">+ provisions. No part of the Material may be used, copied, reproduced, modified,</span><br><span style="color: hsl(120, 100%, 40%);">+ published, uploaded, posted, transmitted, distributed, or disclosed in any way</span><br><span style="color: hsl(120, 100%, 40%);">+ without Intel's prior express written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ No license under any patent, copyright, trade secret or other intellectual</span><br><span style="color: hsl(120, 100%, 40%);">+ property right is granted to or conferred upon you by disclosure or delivery</span><br><span style="color: hsl(120, 100%, 40%);">+ of the Materials, either expressly, by implication, inducement, estoppel or</span><br><span style="color: hsl(120, 100%, 40%);">+ otherwise. Any license under such intellectual property rights must be</span><br><span style="color: hsl(120, 100%, 40%);">+ express and approved by Intel in writing.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ Unless otherwise agreed by Intel in writing, you may not remove or alter</span><br><span style="color: hsl(120, 100%, 40%);">+ this notice or any other notice embedded in Materials by Intel or</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel's suppliers or licensors in any way.</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as</span><br><span style="color: hsl(120, 100%, 40%);">+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under</span><br><span style="color: hsl(120, 100%, 40%);">+ the terms of your license agreement with Intel or your vendor. This file may</span><br><span style="color: hsl(120, 100%, 40%);">+ be modified by the user, subject to additional terms of the license agreement.</span><br><span> </span><br><span> @par Specification Reference:</span><br><span> **/</span><br><span>@@ -63,9 +77,10 @@</span><br><span> UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.</span><br><span> UINT32 RsvdBits : 15; ///< Reserved for future use</span><br><span> UINT32 Reserved;</span><br><span style="color: hsl(0, 100%, 40%);">- } Bits;</span><br><span style="color: hsl(0, 100%, 40%);">- UINT32 Uint32[2];</span><br><span style="color: hsl(0, 100%, 40%);">-} CPU_CONFIG_FSP_DATA;</span><br><span style="color: hsl(120, 100%, 40%);">+ } Bits;</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 Uint32[2];</span><br><span style="color: hsl(120, 100%, 40%);">+ } CPU_CONFIG_FSP_DATA;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #pragma pack (pop)</span><br><span> </span><br><span> #endif // _CPU_CONFIG_FSP_DATA_H_</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h</span><br><span>index bea3509..9fe4972 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h</span><br><span>@@ -1,6 +1,7 @@</span><br><span> /** @file</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+ @copyright</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span> </span><br><span> Redistribution and use in source and binary forms, with or without modification,</span><br><span> are permitted provided that the following conditions are met:</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h</span><br><span>index 5d9e0c2..e7c6839 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h</span><br><span>@@ -1,6 +1,7 @@</span><br><span> /** @file</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+ @copyright</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span> </span><br><span> Redistribution and use in source and binary forms, with or without modification,</span><br><span> are permitted provided that the following conditions are met:</span><br><span>@@ -741,7 +742,7 @@</span><br><span> </span><br><span> /** Offset 0x02CF - Maximum Core Turbo Ratio Override</span><br><span> Maximum core turbo ratio override allows to increase CPU core frequency beyond the</span><br><span style="color: hsl(0, 100%, 40%);">- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83</span><br><span style="color: hsl(120, 100%, 40%);">+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255</span><br><span> **/</span><br><span> UINT8 CoreMaxOcRatio;</span><br><span> </span><br><span>@@ -752,13 +753,13 @@</span><br><span> UINT8 CoreVoltageMode;</span><br><span> </span><br><span> /** Offset 0x02D1 - Minimum clr turbo ratio override</span><br><span style="color: hsl(0, 100%, 40%);">- Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83</span><br><span style="color: hsl(120, 100%, 40%);">+ Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-255</span><br><span> **/</span><br><span> UINT8 RingMinOcRatio;</span><br><span> </span><br><span> /** Offset 0x02D2 - Maximum clr turbo ratio override</span><br><span> Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the</span><br><span style="color: hsl(0, 100%, 40%);">- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83</span><br><span style="color: hsl(120, 100%, 40%);">+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255</span><br><span> **/</span><br><span> UINT8 RingMaxOcRatio;</span><br><span> </span><br><span>@@ -905,11 +906,26 @@</span><br><span> **/</span><br><span> UINT8 FlashWearOutProtection;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0301 - ReservedSecurityPreMem</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0301 - Thermal Velocity Boost Ratio clipping</span><br><span style="color: hsl(120, 100%, 40%);">+ 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction</span><br><span style="color: hsl(120, 100%, 40%);">+ caused by high package temperatures for processors that implement the Intel Thermal</span><br><span style="color: hsl(120, 100%, 40%);">+ Velocity Boost (TVB) feature</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TvbRatioClipping;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0302 - Thermal Velocity Boost voltage optimization</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations</span><br><span style="color: hsl(120, 100%, 40%);">+ for processors that implement the Intel Thermal Velocity Boost (TVB) feature.</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: Disabled, 1: Enabled</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TvbVoltageOptimization;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0303 - ReservedSecurityPreMem</span><br><span> Reserved for Security Pre-Mem</span><br><span> $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedSecurityPreMem[9];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedSecurityPreMem[7];</span><br><span> </span><br><span> /** Offset 0x030A - PCH HPET Enabled</span><br><span> Enable/disable PCH HPET.</span><br><span>@@ -1261,9 +1277,15 @@</span><br><span> **/</span><br><span> UINT8 CleanMemory;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x051C</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x051C - TjMax Offset</span><br><span style="color: hsl(120, 100%, 40%);">+ TjMax offset. Specified value here is clipped by pCode (125 - TjMax Offset) to support</span><br><span style="color: hsl(120, 100%, 40%);">+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 0 - 63</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 ReservedFspmUpd[4];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 TjMaxOffset;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x051D</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 ReservedFspmUpd[3];</span><br><span> } FSP_M_CONFIG;</span><br><span> </span><br><span> /** Fsp M Test Configuration</span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h</span><br><span>index 0209245..39a08d7 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h</span><br><span>@@ -1,6 +1,7 @@</span><br><span> /** @file</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+ @copyright</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright (c) 2018, Intel Corporation. All rights reserved.<BR></span><br><span> </span><br><span> Redistribution and use in source and binary forms, with or without modification,</span><br><span> are permitted provided that the following conditions are met:</span><br><span>@@ -513,9 +514,8 @@</span><br><span> UINT8 PavpEnable;</span><br><span> </span><br><span> /** Offset 0x0216 - CdClock Frequency selection</span><br><span style="color: hsl(0, 100%, 40%);">- 0=308.57 Mhz, 1=337.5 Mhz, 2=432 Mhz, 3=450 Mhz, 4=540 Mhz, 5=617.14 Mhz, 6(Default)= 675 Mhz</span><br><span style="color: hsl(0, 100%, 40%);">- 0: 308.57 Mhz, 1: 337.5 Mhz, 2: 432 Mhz, 3: 450 Mhz, 4: 540 Mhz, 5: 617.14 Mhz,</span><br><span style="color: hsl(0, 100%, 40%);">- 6: 675 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)= 675 Mhz</span><br><span style="color: hsl(120, 100%, 40%);">+ 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz</span><br><span> **/</span><br><span> UINT8 CdClock;</span><br><span> </span><br><span>@@ -538,7 +538,7 @@</span><br><span> UINT8 GmmEnable;</span><br><span> </span><br><span> /** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table</span><br><span style="color: hsl(0, 100%, 40%);">- 0=Disable/Clear, 1(Default)=Enable/Set</span><br><span style="color: hsl(120, 100%, 40%);">+ 0=Disable/Clear, 1=Enable/Set</span><br><span> $EN_DIS</span><br><span> **/</span><br><span> UINT8 X2ApicOptOut;</span><br><span>@@ -670,9 +670,16 @@</span><br><span> **/</span><br><span> UINT16 TdcPowerLimit[5];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0290</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0290 - CPU VR Power Delivery Design</span><br><span style="color: hsl(120, 100%, 40%);">+ Used to communicate the power delivery design capability of the board. This value</span><br><span style="color: hsl(120, 100%, 40%);">+ is an enum of the available power delivery segments that are defined in the Platform</span><br><span style="color: hsl(120, 100%, 40%);">+ Design Guide.</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace11[8];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT32 VrPowerDeliveryDesign;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0294</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace11[4];</span><br><span> </span><br><span> /** Offset 0x0298 - AcLoadline</span><br><span> PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is</span><br><span>@@ -1980,9 +1987,15 @@</span><br><span> **/</span><br><span> UINT8 SataRstOptaneMemory;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-/** Offset 0x0721</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0721 - PCH SATA RST CPU attached storage</span><br><span style="color: hsl(120, 100%, 40%);">+ RST CPU attached storage</span><br><span style="color: hsl(120, 100%, 40%);">+ $EN_DIS</span><br><span> **/</span><br><span style="color: hsl(0, 100%, 40%);">- UINT8 UnusedUpdSpace19[3];</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 SataRstCpuAttachedStorage;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/** Offset 0x0722</span><br><span style="color: hsl(120, 100%, 40%);">+**/</span><br><span style="color: hsl(120, 100%, 40%);">+ UINT8 UnusedUpdSpace19[2];</span><br><span> </span><br><span> /** Offset 0x0724 - Pch PCIE device override table pointer</span><br><span> The PCIe device table is being used to override PCIe device ASPM settings. This</span><br><span>@@ -2170,31 +2183,28 @@</span><br><span> UINT8 SaPostMemTestRsvd[11];</span><br><span> </span><br><span> /** Offset 0x079C - 1-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,</span><br><span style="color: hsl(0, 100%, 40%);">- 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 1-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 1-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,</span><br><span style="color: hsl(120, 100%, 40%);">+ 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,</span><br><span style="color: hsl(120, 100%, 40%);">+ 8-Core Ratio Limit. Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 OneCoreRatioLimit;</span><br><span> </span><br><span> /** Offset 0x079D - 2-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 2-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 2-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 TwoCoreRatioLimit;</span><br><span> </span><br><span> /** Offset 0x079E - 3-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 3-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 3-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 ThreeCoreRatioLimit;</span><br><span> </span><br><span> /** Offset 0x079F - 4-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 4-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 4-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 FourCoreRatioLimit;</span><br><span> </span><br><span>@@ -2771,30 +2781,26 @@</span><br><span> UINT32 CpuS3ResumeData;</span><br><span> </span><br><span> /** Offset 0x0884 - 5-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 5-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 5-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 FiveCoreRatioLimit;</span><br><span> </span><br><span> /** Offset 0x0885 - 6-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 6-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 6-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 SixCoreRatioLimit;</span><br><span> </span><br><span> /** Offset 0x0886 - 7-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 7-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 7-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 SevenCoreRatioLimit;</span><br><span> </span><br><span> /** Offset 0x0887 - 8-Core Ratio Limit</span><br><span style="color: hsl(0, 100%, 40%);">- 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused</span><br><span style="color: hsl(0, 100%, 40%);">- 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal</span><br><span style="color: hsl(0, 100%, 40%);">- to 1-Core Ratio Limit.Range is 0 to 83</span><br><span style="color: hsl(120, 100%, 40%);">+ 8-Core Ratio Limit: LFM to Fused max, For overclocking part: LFM to 255. This 8-Core</span><br><span style="color: hsl(120, 100%, 40%);">+ Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255</span><br><span> **/</span><br><span> UINT8 EightCoreRatioLimit;</span><br><span> </span><br><span>diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h</span><br><span>index 248b4d5..11f79ca 100644</span><br><span>--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h</span><br><span>+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h</span><br><span>@@ -1,33 +1,38 @@</span><br><span> /** @file</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains definitions required for creation of</span><br><span style="color: hsl(120, 100%, 40%);">+ Memory S3 Save data, Memory Info data and Memory Platform</span><br><span style="color: hsl(120, 100%, 40%);">+ data hobs.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR></span><br><span style="color: hsl(120, 100%, 40%);">+ @copyright</span><br><span style="color: hsl(120, 100%, 40%);">+ INTEL CONFIDENTIAL</span><br><span style="color: hsl(120, 100%, 40%);">+ Copyright 1999 - 2017 Intel Corporation.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-Redistribution and use in source and binary forms, with or without modification,</span><br><span style="color: hsl(0, 100%, 40%);">-are permitted provided that the following conditions are met:</span><br><span style="color: hsl(120, 100%, 40%);">+ The source code contained or described herein and all documents related to the</span><br><span style="color: hsl(120, 100%, 40%);">+ source code ("Material") are owned by Intel Corporation or its suppliers or</span><br><span style="color: hsl(120, 100%, 40%);">+ licensors. Title to the Material remains with Intel Corporation or its suppliers</span><br><span style="color: hsl(120, 100%, 40%);">+ and licensors. The Material may contain trade secrets and proprietary and</span><br><span style="color: hsl(120, 100%, 40%);">+ confidential information of Intel Corporation and its suppliers and licensors,</span><br><span style="color: hsl(120, 100%, 40%);">+ and is protected by worldwide copyright and trade secret laws and treaty</span><br><span style="color: hsl(120, 100%, 40%);">+ provisions. No part of the Material may be used, copied, reproduced, modified,</span><br><span style="color: hsl(120, 100%, 40%);">+ published, uploaded, posted, transmitted, distributed, or disclosed in any way</span><br><span style="color: hsl(120, 100%, 40%);">+ without Intel's prior express written permission.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-* Redistributions of source code must retain the above copyright notice, this</span><br><span style="color: hsl(0, 100%, 40%);">- list of conditions and the following disclaimer.</span><br><span style="color: hsl(0, 100%, 40%);">-* Redistributions in binary form must reproduce the above copyright notice, this</span><br><span style="color: hsl(0, 100%, 40%);">- list of conditions and the following disclaimer in the documentation and/or</span><br><span style="color: hsl(0, 100%, 40%);">- other materials provided with the distribution.</span><br><span style="color: hsl(0, 100%, 40%);">-* Neither the name of Intel Corporation nor the names of its contributors may</span><br><span style="color: hsl(0, 100%, 40%);">- be used to endorse or promote products derived from this software without</span><br><span style="color: hsl(0, 100%, 40%);">- specific prior written permission.</span><br><span style="color: hsl(120, 100%, 40%);">+ No license under any patent, copyright, trade secret or other intellectual</span><br><span style="color: hsl(120, 100%, 40%);">+ property right is granted to or conferred upon you by disclosure or delivery</span><br><span style="color: hsl(120, 100%, 40%);">+ of the Materials, either expressly, by implication, inducement, estoppel or</span><br><span style="color: hsl(120, 100%, 40%);">+ otherwise. Any license under such intellectual property rights must be</span><br><span style="color: hsl(120, 100%, 40%);">+ express and approved by Intel in writing.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"</span><br><span style="color: hsl(0, 100%, 40%);">- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE</span><br><span style="color: hsl(0, 100%, 40%);">- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE</span><br><span style="color: hsl(0, 100%, 40%);">- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE</span><br><span style="color: hsl(0, 100%, 40%);">- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR</span><br><span style="color: hsl(0, 100%, 40%);">- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF</span><br><span style="color: hsl(0, 100%, 40%);">- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS</span><br><span style="color: hsl(0, 100%, 40%);">- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN</span><br><span style="color: hsl(0, 100%, 40%);">- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)</span><br><span style="color: hsl(0, 100%, 40%);">- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF</span><br><span style="color: hsl(0, 100%, 40%);">- THE POSSIBILITY OF SUCH DAMAGE.</span><br><span style="color: hsl(120, 100%, 40%);">+ Unless otherwise agreed by Intel in writing, you may not remove or alter</span><br><span style="color: hsl(120, 100%, 40%);">+ this notice or any other notice embedded in Materials by Intel or</span><br><span style="color: hsl(120, 100%, 40%);">+ Intel's suppliers or licensors in any way.</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- This file is automatically generated. Please do NOT modify !!!</span><br><span style="color: hsl(120, 100%, 40%);">+ This file contains an 'Intel Peripheral Driver' and is uniquely identified as</span><br><span style="color: hsl(120, 100%, 40%);">+ "Intel Reference Module" and is licensed for Intel CPUs and chipsets under</span><br><span style="color: hsl(120, 100%, 40%);">+ the terms of your license agreement with Intel or your vendor. This file may</span><br><span style="color: hsl(120, 100%, 40%);">+ be modified by the user, subject to additional terms of the license agreement.</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+@par Specification Reference:</span><br><span> **/</span><br><span> #ifndef _MEM_INFO_HOB_H_</span><br><span> #define _MEM_INFO_HOB_H_</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26665">change 26665</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/26665"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7db337bee80cb6a34d0f65d2cd7b9541c7aead94 </div>
<div style="display:none"> Gerrit-Change-Number: 26665 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Balaji Manigandan <balaji.manigandan@intel.com> </div>