[coreboot-gerrit] Change in coreboot[master]: src/northbridge: Get rid of whitespace befor tab
Elyes HAOUAS (Code Review)
gerrit at coreboot.org
Mon May 28 11:21:49 CEST 2018
Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/26603
Change subject: src/northbridge: Get rid of whitespace befor tab
......................................................................
src/northbridge: Get rid of whitespace befor tab
Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
M src/northbridge/amd/agesa/family14/chip.h
M src/northbridge/amd/amdfam10/resourcemap.c
M src/northbridge/amd/amdht/h3gtopo.h
M src/northbridge/amd/amdk8/f.h
M src/northbridge/amd/amdk8/incoherent_ht.c
M src/northbridge/amd/amdk8/northbridge.c
M src/northbridge/amd/amdk8/raminit.c
M src/northbridge/amd/amdk8/raminit_f.c
M src/northbridge/amd/amdmct/amddefs.h
M src/northbridge/amd/amdmct/mct/mct_d.c
M src/northbridge/amd/amdmct/mct/mct_d_gcc.c
M src/northbridge/amd/amdmct/mct/mctdqs_d.c
M src/northbridge/amd/amdmct/mct/mctecc_d.c
M src/northbridge/amd/amdmct/mct/mctmtr_d.c
M src/northbridge/amd/amdmct/mct/mctsrc.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
M src/northbridge/amd/lx/northbridgeinit.c
M src/northbridge/amd/lx/raminit.c
M src/northbridge/intel/e7505/e7505.h
M src/northbridge/via/cx700/early_smbus.c
M src/northbridge/via/cx700/raminit.c
M src/northbridge/via/vx800/dram_init.h
M src/northbridge/via/vx800/driving_setting.c
M src/northbridge/via/vx800/early_smbus.c
M src/northbridge/via/vx800/uma_ram_setting.c
31 files changed, 63 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/26603/1
diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h
index c3cd965..211ee24 100644
--- a/src/northbridge/amd/agesa/family14/chip.h
+++ b/src/northbridge/amd/agesa/family14/chip.h
@@ -26,8 +26,8 @@
*
* register "spdAddrLookup" = "
* { // Use 8-bit SPD addresses here
- * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1
- * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
+ * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1
+ * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
* }"
*
*/
diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c
index be6f0ef..5db6886 100644
--- a/src/northbridge/amd/amdfam10/resourcemap.c
+++ b/src/northbridge/amd/amdfam10/resourcemap.c
@@ -123,7 +123,7 @@
* [31: 8] Memory-Mapped I/O Limit Address i (39-16)
* This field defines the upp adddress bits of a 40-bit
* address that defines the end of a memory-mapped
- * I/O region n
+ * I/O region n
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,
@@ -158,7 +158,7 @@
* [ 7: 4] Reserved
* [31: 8] Memory-Mapped I/O Base Address i (39-16)
* This field defines the upper address bits of a 40bit
- * address that defines the start of memory-mapped
+ * address that defines the start of memory-mapped
* I/O region i
*/
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,
diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h
index 58673aa..7baba30 100644
--- a/src/northbridge/amd/amdht/h3gtopo.h
+++ b/src/northbridge/amd/amdht/h3gtopo.h
@@ -256,7 +256,7 @@
0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3
0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4
0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5
- 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
+ 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6
};
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index 9f09620..6484fbb 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -89,7 +89,7 @@
#define DRAM_TIMING_LOW 0x88
#define DTL_TCL_SHIFT 0
#define DTL_TCL_MASK 7
-#define DTL_TCL_BASE 1
+#define DTL_TCL_BASE 1
#define DTL_TCL_MIN 3
#define DTL_TCL_MAX 6
#define DTL_TRCD_SHIFT 4
@@ -220,7 +220,7 @@
#define DCH_PowerDownMode_ChipSelect_CKE 1
#define DCH_FourRankSODimm (1<<17)
#define DCH_FourRankRDimm (1<<18)
-#define DCH_SlowAccessMode (1<<19)
+#define DCH_SlowAccessMode (1<<19)
#define DCH_BankSwizzleMode (1<<22)
#define DCH_DcqBypassMax_SHIFT 24
#define DCH_DcqBypassMax_MASK 0xf
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index c1b6802..7b10a3d 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -1,5 +1,5 @@
/*
- This should be done by Eric
+ This should be done by Eric
2004.12 yhlu add multi ht chain dynamically support
2005.11 yhlu add let real sb to use small unitid
*/
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index 4d37098..3286d16 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -981,7 +981,7 @@
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
if (!is_cpu_pre_e0())
#endif
- sizek += hoist_memory(mmio_basek,i);
+ sizek += hoist_memory(mmio_basek,i);
#endif
basek = mmio_basek;
@@ -1206,13 +1206,13 @@
if (j == 0) {
#if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)
- e0_later_single_core = is_e0_later_in_bsp(i); // single core
+ e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
- e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
+ e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3
#endif
} else {
e0_later_single_core = 0;
- }
+ }
if (e0_later_single_core) {
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
@@ -1226,7 +1226,7 @@
}
} else {
siblings = j;
- }
+ }
}
u32 jj;
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index dae1584..1558832 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -1296,7 +1296,7 @@
uint8_t dtl_twr;
uint8_t dtl_twtr;
uint8_t dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */
- uint8_t rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
+ uint8_t rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
char name[9];
};
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 39c5ad8..5d777bf 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -230,7 +230,7 @@
/* DRAM Control Register
* F2:0x78
* [ 3: 0] RdPtrInit (Read Pointer Initial Value)
- * 0x03-0x00: reserved
+ * 0x03-0x00: reserved
* [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
* 000 = reserved
* 001 = reserved
@@ -277,7 +277,7 @@
* EMRS command defined by the MrsAddress and MrsBank fields. This
* bit is cleared by the hardware after the command completes
* [27:27] DeassertMemRstX (De-assert Memory Reset)
- * Setting this bit causes the DRAM controller to de-assert the
+ * Setting this bit causes the DRAM controller to de-assert the
* memory reset pin. This bit cannot be used to assert the memory
* reset pin
* [28:28] AssertCke (Assert CKE)
@@ -462,7 +462,7 @@
* 1 = Enable address parity computation output, PAR,
* and enables the parity error input, ERR
* [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
- * 1 = Enable high temperature (two times normal)
+ * 1 = Enable high temperature (two times normal)
* self refresh rate
* [10:10] BurstLength32 (DRAM Burst Length Set for 32 Bytes)
* 0 = 64-byte mode
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index 58f43f1..971fa35 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -71,10 +71,10 @@
#define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex)
#define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex)
#define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)
-#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
+#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))
#define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))
#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1)
-#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
+#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0)
#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2)
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 8bee434..414f278 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -3752,10 +3752,10 @@
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
- * - a) Disable Compensation (F2[1, 0]9C_x08[30])
- * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
- * c) Do frequency change
- * d) Enable Compensation (F2[1, 0]9C_x08[30])
+ * - a) Disable Compensation (F2[1, 0]9C_x08[30])
+ * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
+ * c) Do frequency change
+ * d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0
diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
index 59618f6..d826fed 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c
@@ -218,7 +218,7 @@
// set fs and use fs prefix to access the mem
__asm__ volatile (
"outb %%al, $0xed\n\t" /* _EXECFENCE */
- "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
+ "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line
"movl %%fs:-64(%%esi), %%eax\n\t" //+1
"movl %%fs:(%%esi), %%eax\n\t" //+2
"movl %%fs:64(%%esi), %%eax\n\t" //+3
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 7140007..9bb87bb 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -461,7 +461,7 @@
continue;
}
- BanksPresent = 1; /* flag for at least one bank is present */
+ BanksPresent = 1; /* flag for at least one bank is present */
TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid);
if (!valid) {
print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);
@@ -762,7 +762,7 @@
test_buf += 2;
}
- bytelane = 0; /* bytelane counter */
+ bytelane = 0; /* bytelane counter */
bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */
for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
value = read32_fs(addr_lo);
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 9b22c84..18774eb 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -96,7 +96,7 @@
OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */
- OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
+ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
nvbits = mctGet_NVbits(NV_DCBKScrub);
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index deb0f8a..1e47ab4 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -36,11 +36,11 @@
/* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space.
* Bottom40bIO = top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Bottom32bIO = sub 4GB top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Cache32bTOP = sub 4GB top of WB cacheable memory,
- * right justified 8 bits
+ * right justified 8 bits
*/
val = mctGet_NVbits(NV_BottomIO);
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 60857f4..3b802f1 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -450,7 +450,7 @@
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index da803ff..6971bfc 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2346,7 +2346,7 @@
enable_slow_access_mode = 1;
}
- reg = 0x94; /* DRAM Configuration High */
+ reg = 0x94; /* DRAM Configuration High */
dword = Get_NB32_DCT(dev, dct, reg);
if (enable_slow_access_mode)
dword |= (0x1 << 20); /* Set 2T CMD mode */
@@ -2539,7 +2539,7 @@
uint32_t dword;
dword = Get_NB32(pDCTstat->dev_dct, 0x118);
- dword &= ~(0x1 << 18); /* CC6SaveEn = enable */
+ dword &= ~(0x1 << 18); /* CC6SaveEn = enable */
dword |= (enable & 0x1) << 18;
Set_NB32(pDCTstat->dev_dct, 0x118, dword);
}
@@ -7908,10 +7908,10 @@
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
- * - a) Disable Compensation (F2[1, 0]9C_x08[30])
- * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
- * c) Do frequency change
- * d) Enable Compensation (F2[1, 0]9C_x08[30])
+ * - a) Disable Compensation (F2[1, 0]9C_x08[30])
+ * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
+ * c) Do frequency change
+ * d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index d4b3792..b5c0b6c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -134,7 +134,7 @@
#define MemClkFreqVal ((is_fam15h())?7:3) /* func 2, offset 94h, bit 3 or 7*/
#define RDqsEn 12 /* func 2, offset 94h, bit 12*/
#define DisDramInterface 14 /* func 2, offset 94h, bit 14*/
-#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/
+#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/
#define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/
#define DctAccessDone 31 /* func 2, offset 98h, bit 31*/
#define MemClrStatus 0 /* func 2, offset A0h, bit 0*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index f751733..9b74817 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -1102,7 +1102,7 @@
dword = Get_NB32_DCT(dev, dct, 0x270);
dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */
-// dword |= (0x55555);
+// dword |= (0x55555);
dword |= (0x44443); /* Use AGESA seed */
Set_NB32_DCT(dev, dct, 0x270, dword);
@@ -1199,7 +1199,7 @@
dword = Get_NB32_DCT(dev, dct, 0x270);
dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */
-// dword |= (0x55555);
+// dword |= (0x55555);
dword |= (0x44443); /* Use AGESA seed */
Set_NB32_DCT(dev, dct, 0x270, dword);
@@ -1633,7 +1633,7 @@
uint8_t lane_training_success[MAX_BYTE_LANES];
uint8_t dqs_results_array[1024];
- uint16_t ren_step = 0x40;
+ uint16_t ren_step = 0x40;
uint32_t index_reg = 0x98;
uint32_t dev = pDCTstat->dev_dct;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 9aad96c..31c23b9 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -115,12 +115,12 @@
OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */
- OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
+ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */
OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
if (!is_fam15h()) {
nvbits = mctGet_NVbits(NV_DCBKScrub);
- /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */
+ /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */
OF_ScrubCTL |= (u32) nvbits << 16;
nvbits = mctGet_NVbits(NV_L2BKScrub);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
index 8a1f736..2bf8562 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
@@ -40,11 +40,11 @@
/* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space.
* Bottom40bIO = top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Bottom32bIO = sub 4GB top of memory, right justified 8 bits
- * (defines dram versus IO space type)
+ * (defines dram versus IO space type)
* Cache32bTOP = sub 4GB top of WB cacheable memory,
- * right justified 8 bits
+ * right justified 8 bits
*/
val = mctGet_NVbits(NV_BottomIO);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 984f604..9312b04 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1002,7 +1002,7 @@
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
@@ -1505,7 +1505,7 @@
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
@@ -1725,7 +1725,7 @@
}
if (!_SSE2) {
cr4 = read_cr4();
- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 4100b26..14debd5 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -696,7 +696,7 @@
* For now, skip restoration...
*/
// for (i = 0; i < 8; i++)
- // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
+ // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
wrmsr_uint64_t(0x000002ff, data->msr000002ff);
wrmsr_uint64_t(0xc0010010, data->msrc0010010);
wrmsr_uint64_t(0xc001001a, data->msrc001001a);
diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c
index f588ead..6eb2cce 100644
--- a/src/northbridge/amd/lx/northbridgeinit.c
+++ b/src/northbridge/amd/lx/northbridgeinit.c
@@ -594,7 +594,7 @@
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
- * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
+ * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
*
***************************************************************************/
#define SYSMEM_RCONF_WRITETHROUGH 8
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 3be0248..7217a78 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -419,8 +419,8 @@
/* tRC = tRP + tRAS */
dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
- ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
- << CF8F_LOWER_ACT2ACTREF_SHIFT;
+ ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
+ << CF8F_LOWER_ACT2ACTREF_SHIFT;
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= 0xF00000FF;
diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h
index 9c9171d..e81e1d6 100644
--- a/src/northbridge/intel/e7505/e7505.h
+++ b/src/northbridge/intel/e7505/e7505.h
@@ -26,7 +26,7 @@
#define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */
#define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */
-#define PAM_0 0x59
+#define PAM_0 0x59
#define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */
#define DRB_ROW_1 0x61
diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c
index 84a0de1..346fb63 100644
--- a/src/northbridge/via/cx700/early_smbus.c
+++ b/src/northbridge/via/cx700/early_smbus.c
@@ -27,7 +27,7 @@
#define SMBBLKDAT SMBUS_IO_BASE + 0x7
#define SMBSLVCTL SMBUS_IO_BASE + 0x8
#define SMBTRNSADD SMBUS_IO_BASE + 0x9
-#define SMBSLVDATA SMBUS_IO_BASE + 0xa
+#define SMBSLVDATA SMBUS_IO_BASE + 0xa
#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index 682f3be..9a9450c 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -208,9 +208,9 @@
#define DDR2_ODT_150ohm 0x40
static const u8 ODT_TBL[] = {
-/* RankMap, ODT Control Bits, DRAM & NB ODT setting */
+/* RankMap, ODT Control Bits, DRAM & NB ODT setting */
0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
- 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
+ 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),
0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),
diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h
index 3e3f6af..aa509c1 100644
--- a/src/northbridge/via/vx800/dram_init.h
+++ b/src/northbridge/via/vx800/dram_init.h
@@ -26,7 +26,7 @@
#define M512 (512*M)
// UMA size
-#define UMASIZE M64
+#define UMASIZE M64
#define ENABLE_CHC 0 //CHC enable, how ever, this CHC,used some reg define in CHB
#define ENABLE_CHB 0 //CHB enable , CHB is VX800's, VX855 no this CHB.
diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c
index a67c5b0..f702c68 100644
--- a/src/northbridge/via/vx800/driving_setting.c
+++ b/src/northbridge/via/vx800/driving_setting.c
@@ -56,9 +56,9 @@
which include driving enable/range and strong/weak selection
Processing: According to DRAM frequency to ODT control bits.
- Because function enable bit must be the last one to be set.
- So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be
- the last register to be programmed.
+ Because function enable bit must be the last one to be set.
+ So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be
+ the last register to be programmed.
*/
//-------------------------------------------------------------------------------
// ODT Lookup Table
diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c
index 816fe28..3a3a2a6 100644
--- a/src/northbridge/via/vx800/early_smbus.c
+++ b/src/northbridge/via/vx800/early_smbus.c
@@ -30,7 +30,7 @@
#define SMBBLKDAT SMBUS_IO_BASE + 0x7
#define SMBSLVCTL SMBUS_IO_BASE + 0x8
#define SMBTRNSADD SMBUS_IO_BASE + 0x9
-#define SMBSLVDATA SMBUS_IO_BASE + 0xa
+#define SMBSLVDATA SMBUS_IO_BASE + 0xa
#define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe
#define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf
diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c
index c9738da..8745979 100644
--- a/src/northbridge/via/vx800/uma_ram_setting.c
+++ b/src/northbridge/via/vx800/uma_ram_setting.c
@@ -24,7 +24,7 @@
#define UMARAM_512M 7
#define UMARAM_256M 6
#define UMARAM_128M 5
-#define UMARAM_64M 4
+#define UMARAM_64M 4
#define UMARAM_32M 3
#define UMARAM_16M 2
#define UMARAM_8M 1
--
To view, visit https://review.coreboot.org/26603
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935
Gerrit-Change-Number: 26603
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180528/bf8686fe/attachment-0001.html>
More information about the coreboot-gerrit
mailing list