<p>Elyes HAOUAS has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26603">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/northbridge: Get rid of whitespace befor tab<br><br>Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935<br>Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr><br>---<br>M src/northbridge/amd/agesa/family14/chip.h<br>M src/northbridge/amd/amdfam10/resourcemap.c<br>M src/northbridge/amd/amdht/h3gtopo.h<br>M src/northbridge/amd/amdk8/f.h<br>M src/northbridge/amd/amdk8/incoherent_ht.c<br>M src/northbridge/amd/amdk8/northbridge.c<br>M src/northbridge/amd/amdk8/raminit.c<br>M src/northbridge/amd/amdk8/raminit_f.c<br>M src/northbridge/amd/amdmct/amddefs.h<br>M src/northbridge/amd/amdmct/mct/mct_d.c<br>M src/northbridge/amd/amdmct/mct/mct_d_gcc.c<br>M src/northbridge/amd/amdmct/mct/mctdqs_d.c<br>M src/northbridge/amd/amdmct/mct/mctecc_d.c<br>M src/northbridge/amd/amdmct/mct/mctmtr_d.c<br>M src/northbridge/amd/amdmct/mct/mctsrc.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mct_d.h<br>M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c<br>M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c<br>M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c<br>M src/northbridge/amd/lx/northbridgeinit.c<br>M src/northbridge/amd/lx/raminit.c<br>M src/northbridge/intel/e7505/e7505.h<br>M src/northbridge/via/cx700/early_smbus.c<br>M src/northbridge/via/cx700/raminit.c<br>M src/northbridge/via/vx800/dram_init.h<br>M src/northbridge/via/vx800/driving_setting.c<br>M src/northbridge/via/vx800/early_smbus.c<br>M src/northbridge/via/vx800/uma_ram_setting.c<br>31 files changed, 63 insertions(+), 63 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/26603/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/northbridge/amd/agesa/family14/chip.h b/src/northbridge/amd/agesa/family14/chip.h</span><br><span>index c3cd965..211ee24 100644</span><br><span>--- a/src/northbridge/amd/agesa/family14/chip.h</span><br><span>+++ b/src/northbridge/amd/agesa/family14/chip.h</span><br><span>@@ -26,8 +26,8 @@</span><br><span> *</span><br><span> * register "spdAddrLookup" = "</span><br><span> * { // Use 8-bit SPD addresses here</span><br><span style="color: hsl(0, 100%, 40%);">- * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1</span><br><span style="color: hsl(0, 100%, 40%);">- * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)</span><br><span style="color: hsl(120, 100%, 40%);">+ * { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1</span><br><span style="color: hsl(120, 100%, 40%);">+ * { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)</span><br><span> * }"</span><br><span> *</span><br><span> */</span><br><span>diff --git a/src/northbridge/amd/amdfam10/resourcemap.c b/src/northbridge/amd/amdfam10/resourcemap.c</span><br><span>index be6f0ef..5db6886 100644</span><br><span>--- a/src/northbridge/amd/amdfam10/resourcemap.c</span><br><span>+++ b/src/northbridge/amd/amdfam10/resourcemap.c</span><br><span>@@ -123,7 +123,7 @@</span><br><span> * [31: 8] Memory-Mapped I/O Limit Address i (39-16)</span><br><span> * This field defines the upp adddress bits of a 40-bit</span><br><span> * address that defines the end of a memory-mapped</span><br><span style="color: hsl(0, 100%, 40%);">- * I/O region n</span><br><span style="color: hsl(120, 100%, 40%);">+ * I/O region n</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x84), 0x00000048, 0x00000000,</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x8C), 0x00000048, 0x00000000,</span><br><span>@@ -158,7 +158,7 @@</span><br><span> * [ 7: 4] Reserved</span><br><span> * [31: 8] Memory-Mapped I/O Base Address i (39-16)</span><br><span> * This field defines the upper address bits of a 40bit</span><br><span style="color: hsl(0, 100%, 40%);">- * address that defines the start of memory-mapped</span><br><span style="color: hsl(120, 100%, 40%);">+ * address that defines the start of memory-mapped</span><br><span> * I/O region i</span><br><span> */</span><br><span> PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x80), 0x000000f0, 0x00000000,</span><br><span>diff --git a/src/northbridge/amd/amdht/h3gtopo.h b/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>index 58673aa..7baba30 100644</span><br><span>--- a/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>+++ b/src/northbridge/amd/amdht/h3gtopo.h</span><br><span>@@ -256,7 +256,7 @@</span><br><span> 0x00, 0x41, 0x30, 0x11, 0x00, 0x45, 0x32, 0xFF, 0x02, 0x44, 0x12, 0x55, 0x02, 0x44, // Node3</span><br><span> 0x48, 0x22, 0x40, 0x33, 0x48, 0x22, 0x40, 0x33, 0x4C, 0xFF, 0x40, 0x32, 0x0C, 0x66, // Node4</span><br><span> 0x00, 0x22, 0x04, 0x33, 0x00, 0x22, 0x04, 0x33, 0x00, 0x23, 0x0C, 0xFF, 0x00, 0x23, // Node5</span><br><span style="color: hsl(0, 100%, 40%);">- 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF // Node6</span><br><span> };</span><br><span> </span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h</span><br><span>index 9f09620..6484fbb 100644</span><br><span>--- a/src/northbridge/amd/amdk8/f.h</span><br><span>+++ b/src/northbridge/amd/amdk8/f.h</span><br><span>@@ -89,7 +89,7 @@</span><br><span> #define DRAM_TIMING_LOW 0x88</span><br><span> #define DTL_TCL_SHIFT 0</span><br><span> #define DTL_TCL_MASK 7</span><br><span style="color: hsl(0, 100%, 40%);">-#define DTL_TCL_BASE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define DTL_TCL_BASE 1</span><br><span> #define DTL_TCL_MIN 3</span><br><span> #define DTL_TCL_MAX 6</span><br><span> #define DTL_TRCD_SHIFT 4</span><br><span>@@ -220,7 +220,7 @@</span><br><span> #define DCH_PowerDownMode_ChipSelect_CKE 1</span><br><span> #define DCH_FourRankSODimm (1<<17)</span><br><span> #define DCH_FourRankRDimm (1<<18)</span><br><span style="color: hsl(0, 100%, 40%);">-#define DCH_SlowAccessMode (1<<19)</span><br><span style="color: hsl(120, 100%, 40%);">+#define DCH_SlowAccessMode (1<<19)</span><br><span> #define DCH_BankSwizzleMode (1<<22)</span><br><span> #define DCH_DcqBypassMax_SHIFT 24</span><br><span> #define DCH_DcqBypassMax_MASK 0xf</span><br><span>diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c</span><br><span>index c1b6802..7b10a3d 100644</span><br><span>--- a/src/northbridge/amd/amdk8/incoherent_ht.c</span><br><span>+++ b/src/northbridge/amd/amdk8/incoherent_ht.c</span><br><span>@@ -1,5 +1,5 @@</span><br><span> /*</span><br><span style="color: hsl(0, 100%, 40%);">- This should be done by Eric</span><br><span style="color: hsl(120, 100%, 40%);">+ This should be done by Eric</span><br><span> 2004.12 yhlu add multi ht chain dynamically support</span><br><span> 2005.11 yhlu add let real sb to use small unitid</span><br><span> */</span><br><span>diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c</span><br><span>index 4d37098..3286d16 100644</span><br><span>--- a/src/northbridge/amd/amdk8/northbridge.c</span><br><span>+++ b/src/northbridge/amd/amdk8/northbridge.c</span><br><span>@@ -981,7 +981,7 @@</span><br><span> #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)</span><br><span> if (!is_cpu_pre_e0())</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">- sizek += hoist_memory(mmio_basek,i);</span><br><span style="color: hsl(120, 100%, 40%);">+ sizek += hoist_memory(mmio_basek,i);</span><br><span> #endif</span><br><span> </span><br><span> basek = mmio_basek;</span><br><span>@@ -1206,13 +1206,13 @@</span><br><span> </span><br><span> if (j == 0) {</span><br><span> #if !IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)</span><br><span style="color: hsl(0, 100%, 40%);">- e0_later_single_core = is_e0_later_in_bsp(i); // single core</span><br><span style="color: hsl(120, 100%, 40%);">+ e0_later_single_core = is_e0_later_in_bsp(i); // single core</span><br><span> #else</span><br><span style="color: hsl(0, 100%, 40%);">- e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3</span><br><span style="color: hsl(120, 100%, 40%);">+ e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3</span><br><span> #endif</span><br><span> } else {</span><br><span> e0_later_single_core = 0;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> if (e0_later_single_core) {</span><br><span> printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");</span><br><span> </span><br><span>@@ -1226,7 +1226,7 @@</span><br><span> }</span><br><span> } else {</span><br><span> siblings = j;</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span> }</span><br><span> </span><br><span> u32 jj;</span><br><span>diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c</span><br><span>index dae1584..1558832 100644</span><br><span>--- a/src/northbridge/amd/amdk8/raminit.c</span><br><span>+++ b/src/northbridge/amd/amdk8/raminit.c</span><br><span>@@ -1296,7 +1296,7 @@</span><br><span> uint8_t dtl_twr;</span><br><span> uint8_t dtl_twtr;</span><br><span> uint8_t dtl_trwt[3][3]; /* first index is CAS_LAT 2/2.5/3 and 128/registered64/64 */</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */</span><br><span style="color: hsl(120, 100%, 40%);">+ uint8_t rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */</span><br><span> char name[9];</span><br><span> };</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c</span><br><span>index 39c5ad8..5d777bf 100644</span><br><span>--- a/src/northbridge/amd/amdk8/raminit_f.c</span><br><span>+++ b/src/northbridge/amd/amdk8/raminit_f.c</span><br><span>@@ -230,7 +230,7 @@</span><br><span> /* DRAM Control Register</span><br><span> * F2:0x78</span><br><span> * [ 3: 0] RdPtrInit (Read Pointer Initial Value)</span><br><span style="color: hsl(0, 100%, 40%);">- * 0x03-0x00: reserved</span><br><span style="color: hsl(120, 100%, 40%);">+ * 0x03-0x00: reserved</span><br><span> * [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)</span><br><span> * 000 = reserved</span><br><span> * 001 = reserved</span><br><span>@@ -277,7 +277,7 @@</span><br><span> * EMRS command defined by the MrsAddress and MrsBank fields. This</span><br><span> * bit is cleared by the hardware after the command completes</span><br><span> * [27:27] DeassertMemRstX (De-assert Memory Reset)</span><br><span style="color: hsl(0, 100%, 40%);">- * Setting this bit causes the DRAM controller to de-assert the</span><br><span style="color: hsl(120, 100%, 40%);">+ * Setting this bit causes the DRAM controller to de-assert the</span><br><span> * memory reset pin. This bit cannot be used to assert the memory</span><br><span> * reset pin</span><br><span> * [28:28] AssertCke (Assert CKE)</span><br><span>@@ -462,7 +462,7 @@</span><br><span> * 1 = Enable address parity computation output, PAR,</span><br><span> * and enables the parity error input, ERR</span><br><span> * [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)</span><br><span style="color: hsl(0, 100%, 40%);">- * 1 = Enable high temperature (two times normal)</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1 = Enable high temperature (two times normal)</span><br><span> * self refresh rate</span><br><span> * [10:10] BurstLength32 (DRAM Burst Length Set for 32 Bytes)</span><br><span> * 0 = 64-byte mode</span><br><span>diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h</span><br><span>index 58f43f1..971fa35 100644</span><br><span>--- a/src/northbridge/amd/amdmct/amddefs.h</span><br><span>+++ b/src/northbridge/amd/amdmct/amddefs.h</span><br><span>@@ -71,10 +71,10 @@</span><br><span> #define AMD_DR_GT_D0 ((AMD_DR_Dx & ~(AMD_HY_D0)) | AMD_DR_Ex)</span><br><span> #define AMD_DR_ALL (AMD_DR_Ax | AMD_DR_Bx | AMD_DR_Cx | AMD_DR_Dx | AMD_DR_Ex)</span><br><span> #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2 | AMD_RB_C3 | AMD_HY_D1 | AMD_PH_E0)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))</span><br><span style="color: hsl(120, 100%, 40%);">+#define AMD_FAM10_LT_D (AMD_FAM10_ALL & ~(AMD_HY_D0))</span><br><span> #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0))</span><br><span> #define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1)</span><br><span style="color: hsl(0, 100%, 40%);">-#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)</span><br><span style="color: hsl(120, 100%, 40%);">+#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)</span><br><span> #define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)</span><br><span> #define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0)</span><br><span> #define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2)</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c</span><br><span>index 8bee434..414f278 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mct_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mct_d.c</span><br><span>@@ -3752,10 +3752,10 @@</span><br><span> * Solution: From the bug report:</span><br><span> * 1. A software-initiated frequency change should be wrapped into the</span><br><span> * following sequence :</span><br><span style="color: hsl(0, 100%, 40%);">- * - a) Disable Compensation (F2[1, 0]9C_x08[30])</span><br><span style="color: hsl(0, 100%, 40%);">- * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines</span><br><span style="color: hsl(0, 100%, 40%);">- * c) Do frequency change</span><br><span style="color: hsl(0, 100%, 40%);">- * d) Enable Compensation (F2[1, 0]9C_x08[30])</span><br><span style="color: hsl(120, 100%, 40%);">+ * - a) Disable Compensation (F2[1, 0]9C_x08[30])</span><br><span style="color: hsl(120, 100%, 40%);">+ * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines</span><br><span style="color: hsl(120, 100%, 40%);">+ * c) Do frequency change</span><br><span style="color: hsl(120, 100%, 40%);">+ * d) Enable Compensation (F2[1, 0]9C_x08[30])</span><br><span> * 2. A software-initiated Disable Compensation should always be</span><br><span> * followed by step b) of the above steps.</span><br><span> * Silicon Status: Fixed In Rev B0</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c</span><br><span>index 59618f6..d826fed 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.c</span><br><span>@@ -218,7 +218,7 @@</span><br><span> // set fs and use fs prefix to access the mem</span><br><span> __asm__ volatile (</span><br><span> "outb %%al, $0xed\n\t" /* _EXECFENCE */</span><br><span style="color: hsl(0, 100%, 40%);">- "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line</span><br><span style="color: hsl(120, 100%, 40%);">+ "movl %%fs:-128(%%esi), %%eax\n\t" //TestAddr cache line</span><br><span> "movl %%fs:-64(%%esi), %%eax\n\t" //+1</span><br><span> "movl %%fs:(%%esi), %%eax\n\t" //+2</span><br><span> "movl %%fs:64(%%esi), %%eax\n\t" //+3</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c</span><br><span>index 7140007..9bb87bb 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c</span><br><span>@@ -461,7 +461,7 @@</span><br><span> continue;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- BanksPresent = 1; /* flag for at least one bank is present */</span><br><span style="color: hsl(120, 100%, 40%);">+ BanksPresent = 1; /* flag for at least one bank is present */</span><br><span> TestAddr = mct_GetMCTSysAddr_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel, &valid);</span><br><span> if (!valid) {</span><br><span> print_debug_dqs("\t\t\t\tAddress not supported on current CS ", TestAddr, 4);</span><br><span>@@ -762,7 +762,7 @@</span><br><span> test_buf += 2;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- bytelane = 0; /* bytelane counter */</span><br><span style="color: hsl(120, 100%, 40%);">+ bytelane = 0; /* bytelane counter */</span><br><span> bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */</span><br><span> for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */</span><br><span> value = read32_fs(addr_lo);</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c</span><br><span>index 9b22c84..18774eb 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c</span><br><span>@@ -96,7 +96,7 @@</span><br><span> </span><br><span> OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */</span><br><span> </span><br><span> OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */</span><br><span> nvbits = mctGet_NVbits(NV_DCBKScrub);</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c</span><br><span>index deb0f8a..1e47ab4 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c</span><br><span>@@ -36,11 +36,11 @@</span><br><span> /* Set temporary top of memory from Node structure data.</span><br><span> * Adjust temp top of memory down to accommodate 32-bit IO space.</span><br><span> * Bottom40bIO = top of memory, right justified 8 bits</span><br><span style="color: hsl(0, 100%, 40%);">- * (defines dram versus IO space type)</span><br><span style="color: hsl(120, 100%, 40%);">+ * (defines dram versus IO space type)</span><br><span> * Bottom32bIO = sub 4GB top of memory, right justified 8 bits</span><br><span style="color: hsl(0, 100%, 40%);">- * (defines dram versus IO space type)</span><br><span style="color: hsl(120, 100%, 40%);">+ * (defines dram versus IO space type)</span><br><span> * Cache32bTOP = sub 4GB top of WB cacheable memory,</span><br><span style="color: hsl(0, 100%, 40%);">- * right justified 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ * right justified 8 bits</span><br><span> */</span><br><span> </span><br><span> val = mctGet_NVbits(NV_BottomIO);</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c</span><br><span>index 60857f4..3b802f1 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct/mctsrc.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c</span><br><span>@@ -450,7 +450,7 @@</span><br><span> }</span><br><span> if (!_SSE2) {</span><br><span> cr4 = read_cr4();</span><br><span style="color: hsl(0, 100%, 40%);">- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span style="color: hsl(120, 100%, 40%);">+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span> write_cr4(cr4);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>index da803ff..6971bfc 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c</span><br><span>@@ -2346,7 +2346,7 @@</span><br><span> enable_slow_access_mode = 1;</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg = 0x94; /* DRAM Configuration High */</span><br><span style="color: hsl(120, 100%, 40%);">+ reg = 0x94; /* DRAM Configuration High */</span><br><span> dword = Get_NB32_DCT(dev, dct, reg);</span><br><span> if (enable_slow_access_mode)</span><br><span> dword |= (0x1 << 20); /* Set 2T CMD mode */</span><br><span>@@ -2539,7 +2539,7 @@</span><br><span> uint32_t dword;</span><br><span> </span><br><span> dword = Get_NB32(pDCTstat->dev_dct, 0x118);</span><br><span style="color: hsl(0, 100%, 40%);">- dword &= ~(0x1 << 18); /* CC6SaveEn = enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ dword &= ~(0x1 << 18); /* CC6SaveEn = enable */</span><br><span> dword |= (enable & 0x1) << 18;</span><br><span> Set_NB32(pDCTstat->dev_dct, 0x118, dword);</span><br><span> }</span><br><span>@@ -7908,10 +7908,10 @@</span><br><span> * Solution: From the bug report:</span><br><span> * 1. A software-initiated frequency change should be wrapped into the</span><br><span> * following sequence :</span><br><span style="color: hsl(0, 100%, 40%);">- * - a) Disable Compensation (F2[1, 0]9C_x08[30])</span><br><span style="color: hsl(0, 100%, 40%);">- * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines</span><br><span style="color: hsl(0, 100%, 40%);">- * c) Do frequency change</span><br><span style="color: hsl(0, 100%, 40%);">- * d) Enable Compensation (F2[1, 0]9C_x08[30])</span><br><span style="color: hsl(120, 100%, 40%);">+ * - a) Disable Compensation (F2[1, 0]9C_x08[30])</span><br><span style="color: hsl(120, 100%, 40%);">+ * b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines</span><br><span style="color: hsl(120, 100%, 40%);">+ * c) Do frequency change</span><br><span style="color: hsl(120, 100%, 40%);">+ * d) Enable Compensation (F2[1, 0]9C_x08[30])</span><br><span> * 2. A software-initiated Disable Compensation should always be</span><br><span> * followed by step b) of the above steps.</span><br><span> * Silicon Status: Fixed In Rev B0</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h</span><br><span>index d4b3792..b5c0b6c 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h</span><br><span>@@ -134,7 +134,7 @@</span><br><span> #define MemClkFreqVal ((is_fam15h())?7:3) /* func 2, offset 94h, bit 3 or 7*/</span><br><span> #define RDqsEn 12 /* func 2, offset 94h, bit 12*/</span><br><span> #define DisDramInterface 14 /* func 2, offset 94h, bit 14*/</span><br><span style="color: hsl(0, 100%, 40%);">-#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/</span><br><span style="color: hsl(120, 100%, 40%);">+#define PowerDownEn 15 /* func 2, offset 94h, bit 15*/</span><br><span> #define DctAccessWrite 30 /* func 2, offset 98h, bit 30*/</span><br><span> #define DctAccessDone 31 /* func 2, offset 98h, bit 31*/</span><br><span> #define MemClrStatus 0 /* func 2, offset A0h, bit 0*/</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>index f751733..9b74817 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c</span><br><span>@@ -1102,7 +1102,7 @@</span><br><span> </span><br><span> dword = Get_NB32_DCT(dev, dct, 0x270);</span><br><span> dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */</span><br><span style="color: hsl(0, 100%, 40%);">-// dword |= (0x55555);</span><br><span style="color: hsl(120, 100%, 40%);">+// dword |= (0x55555);</span><br><span> dword |= (0x44443); /* Use AGESA seed */</span><br><span> Set_NB32_DCT(dev, dct, 0x270, dword);</span><br><span> </span><br><span>@@ -1199,7 +1199,7 @@</span><br><span> </span><br><span> dword = Get_NB32_DCT(dev, dct, 0x270);</span><br><span> dword &= ~(0x7ffff); /* DataPrbsSeed = 55555 */</span><br><span style="color: hsl(0, 100%, 40%);">-// dword |= (0x55555);</span><br><span style="color: hsl(120, 100%, 40%);">+// dword |= (0x55555);</span><br><span> dword |= (0x44443); /* Use AGESA seed */</span><br><span> Set_NB32_DCT(dev, dct, 0x270, dword);</span><br><span> </span><br><span>@@ -1633,7 +1633,7 @@</span><br><span> uint8_t lane_training_success[MAX_BYTE_LANES];</span><br><span> uint8_t dqs_results_array[1024];</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- uint16_t ren_step = 0x40;</span><br><span style="color: hsl(120, 100%, 40%);">+ uint16_t ren_step = 0x40;</span><br><span> uint32_t index_reg = 0x98;</span><br><span> uint32_t dev = pDCTstat->dev_dct;</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c</span><br><span>index 9aad96c..31c23b9 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c</span><br><span>@@ -115,12 +115,12 @@</span><br><span> </span><br><span> OB_ECCRedir = mctGet_NVbits(NV_ECCRedir); /* ECC Redirection */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */</span><br><span style="color: hsl(120, 100%, 40%);">+ OB_ChipKill = mctGet_NVbits(NV_ChipKill); /* ECC Chip-kill mode */</span><br><span> OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */</span><br><span> </span><br><span> if (!is_fam15h()) {</span><br><span> nvbits = mctGet_NVbits(NV_DCBKScrub);</span><br><span style="color: hsl(0, 100%, 40%);">- /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* mct_AdjustScrub_D(pDCTstatA, &nvbits); */ /* Need not adjust */</span><br><span> OF_ScrubCTL |= (u32) nvbits << 16;</span><br><span> </span><br><span> nvbits = mctGet_NVbits(NV_L2BKScrub);</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c</span><br><span>index 8a1f736..2bf8562 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c</span><br><span>@@ -40,11 +40,11 @@</span><br><span> /* Set temporary top of memory from Node structure data.</span><br><span> * Adjust temp top of memory down to accommodate 32-bit IO space.</span><br><span> * Bottom40bIO = top of memory, right justified 8 bits</span><br><span style="color: hsl(0, 100%, 40%);">- * (defines dram versus IO space type)</span><br><span style="color: hsl(120, 100%, 40%);">+ * (defines dram versus IO space type)</span><br><span> * Bottom32bIO = sub 4GB top of memory, right justified 8 bits</span><br><span style="color: hsl(0, 100%, 40%);">- * (defines dram versus IO space type)</span><br><span style="color: hsl(120, 100%, 40%);">+ * (defines dram versus IO space type)</span><br><span> * Cache32bTOP = sub 4GB top of WB cacheable memory,</span><br><span style="color: hsl(0, 100%, 40%);">- * right justified 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ * right justified 8 bits</span><br><span> */</span><br><span> </span><br><span> val = mctGet_NVbits(NV_BottomIO);</span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>index 984f604..9312b04 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c</span><br><span>@@ -1002,7 +1002,7 @@</span><br><span> }</span><br><span> if (!_SSE2) {</span><br><span> cr4 = read_cr4();</span><br><span style="color: hsl(0, 100%, 40%);">- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span style="color: hsl(120, 100%, 40%);">+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span> write_cr4(cr4);</span><br><span> }</span><br><span> </span><br><span>@@ -1505,7 +1505,7 @@</span><br><span> }</span><br><span> if (!_SSE2) {</span><br><span> cr4 = read_cr4();</span><br><span style="color: hsl(0, 100%, 40%);">- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span style="color: hsl(120, 100%, 40%);">+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span> write_cr4(cr4);</span><br><span> }</span><br><span> </span><br><span>@@ -1725,7 +1725,7 @@</span><br><span> }</span><br><span> if (!_SSE2) {</span><br><span> cr4 = read_cr4();</span><br><span style="color: hsl(0, 100%, 40%);">- cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span style="color: hsl(120, 100%, 40%);">+ cr4 &= ~(1<<9); /* restore cr4.OSFXSR */</span><br><span> write_cr4(cr4);</span><br><span> }</span><br><span> </span><br><span>diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>index 4100b26..14debd5 100644</span><br><span>--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c</span><br><span>@@ -696,7 +696,7 @@</span><br><span> * For now, skip restoration...</span><br><span> */</span><br><span> // for (i = 0; i < 8; i++)</span><br><span style="color: hsl(0, 100%, 40%);">- // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);</span><br><span style="color: hsl(120, 100%, 40%);">+ // wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);</span><br><span> wrmsr_uint64_t(0x000002ff, data->msr000002ff);</span><br><span> wrmsr_uint64_t(0xc0010010, data->msrc0010010);</span><br><span> wrmsr_uint64_t(0xc001001a, data->msrc001001a);</span><br><span>diff --git a/src/northbridge/amd/lx/northbridgeinit.c b/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>index f588ead..6eb2cce 100644</span><br><span>--- a/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>+++ b/src/northbridge/amd/lx/northbridgeinit.c</span><br><span>@@ -594,7 +594,7 @@</span><br><span> * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area</span><br><span> * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.</span><br><span> * SYSTOP(27:8) = top of system memory</span><br><span style="color: hsl(0, 100%, 40%);">- * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough</span><br><span style="color: hsl(120, 100%, 40%);">+ * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough</span><br><span> *</span><br><span> ***************************************************************************/</span><br><span> #define SYSMEM_RCONF_WRITETHROUGH 8</span><br><span>diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c</span><br><span>index 3be0248..7217a78 100644</span><br><span>--- a/src/northbridge/amd/lx/raminit.c</span><br><span>+++ b/src/northbridge/amd/lx/raminit.c</span><br><span>@@ -419,8 +419,8 @@</span><br><span> </span><br><span> /* tRC = tRP + tRAS */</span><br><span> dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +</span><br><span style="color: hsl(0, 100%, 40%);">- ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))</span><br><span style="color: hsl(0, 100%, 40%);">- << CF8F_LOWER_ACT2ACTREF_SHIFT;</span><br><span style="color: hsl(120, 100%, 40%);">+ ((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))</span><br><span style="color: hsl(120, 100%, 40%);">+ << CF8F_LOWER_ACT2ACTREF_SHIFT;</span><br><span> </span><br><span> msr = rdmsr(MC_CF8F_DATA);</span><br><span> msr.lo &= 0xF00000FF;</span><br><span>diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h</span><br><span>index 9c9171d..e81e1d6 100644</span><br><span>--- a/src/northbridge/intel/e7505/e7505.h</span><br><span>+++ b/src/northbridge/intel/e7505/e7505.h</span><br><span>@@ -26,7 +26,7 @@</span><br><span> #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */</span><br><span> #define MCHCFGNS 0x52 /* MCH (scrubber) configuration register, 16 bit */</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define PAM_0 0x59</span><br><span style="color: hsl(120, 100%, 40%);">+#define PAM_0 0x59</span><br><span> </span><br><span> #define DRB_ROW_0 0x60 /* DRAM Row Boundary register, 8 bit */</span><br><span> #define DRB_ROW_1 0x61</span><br><span>diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c</span><br><span>index 84a0de1..346fb63 100644</span><br><span>--- a/src/northbridge/via/cx700/early_smbus.c</span><br><span>+++ b/src/northbridge/via/cx700/early_smbus.c</span><br><span>@@ -27,7 +27,7 @@</span><br><span> #define SMBBLKDAT SMBUS_IO_BASE + 0x7</span><br><span> #define SMBSLVCTL SMBUS_IO_BASE + 0x8</span><br><span> #define SMBTRNSADD SMBUS_IO_BASE + 0x9</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMBSLVDATA SMBUS_IO_BASE + 0xa</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBSLVDATA SMBUS_IO_BASE + 0xa</span><br><span> #define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe</span><br><span> #define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf</span><br><span> </span><br><span>diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c</span><br><span>index 682f3be..9a9450c 100644</span><br><span>--- a/src/northbridge/via/cx700/raminit.c</span><br><span>+++ b/src/northbridge/via/cx700/raminit.c</span><br><span>@@ -208,9 +208,9 @@</span><br><span> #define DDR2_ODT_150ohm 0x40</span><br><span> </span><br><span> static const u8 ODT_TBL[] = {</span><br><span style="color: hsl(0, 100%, 40%);">-/* RankMap, ODT Control Bits, DRAM & NB ODT setting */</span><br><span style="color: hsl(120, 100%, 40%);">+/* RankMap, ODT Control Bits, DRAM & NB ODT setting */</span><br><span> 0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),</span><br><span style="color: hsl(0, 100%, 40%);">- 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),</span><br><span style="color: hsl(120, 100%, 40%);">+ 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),</span><br><span> 0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm),</span><br><span> 0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),</span><br><span> 0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm),</span><br><span>diff --git a/src/northbridge/via/vx800/dram_init.h b/src/northbridge/via/vx800/dram_init.h</span><br><span>index 3e3f6af..aa509c1 100644</span><br><span>--- a/src/northbridge/via/vx800/dram_init.h</span><br><span>+++ b/src/northbridge/via/vx800/dram_init.h</span><br><span>@@ -26,7 +26,7 @@</span><br><span> #define M512 (512*M)</span><br><span> </span><br><span> // UMA size</span><br><span style="color: hsl(0, 100%, 40%);">-#define UMASIZE M64</span><br><span style="color: hsl(120, 100%, 40%);">+#define UMASIZE M64</span><br><span> </span><br><span> #define ENABLE_CHC 0 //CHC enable, how ever, this CHC,used some reg define in CHB</span><br><span> #define ENABLE_CHB 0 //CHB enable , CHB is VX800's, VX855 no this CHB.</span><br><span>diff --git a/src/northbridge/via/vx800/driving_setting.c b/src/northbridge/via/vx800/driving_setting.c</span><br><span>index a67c5b0..f702c68 100644</span><br><span>--- a/src/northbridge/via/vx800/driving_setting.c</span><br><span>+++ b/src/northbridge/via/vx800/driving_setting.c</span><br><span>@@ -56,9 +56,9 @@</span><br><span> which include driving enable/range and strong/weak selection</span><br><span> </span><br><span> Processing: According to DRAM frequency to ODT control bits.</span><br><span style="color: hsl(0, 100%, 40%);">- Because function enable bit must be the last one to be set.</span><br><span style="color: hsl(0, 100%, 40%);">- So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be</span><br><span style="color: hsl(0, 100%, 40%);">- the last register to be programmed.</span><br><span style="color: hsl(120, 100%, 40%);">+ Because function enable bit must be the last one to be set.</span><br><span style="color: hsl(120, 100%, 40%);">+ So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be</span><br><span style="color: hsl(120, 100%, 40%);">+ the last register to be programmed.</span><br><span> */</span><br><span> //-------------------------------------------------------------------------------</span><br><span> // ODT Lookup Table</span><br><span>diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c</span><br><span>index 816fe28..3a3a2a6 100644</span><br><span>--- a/src/northbridge/via/vx800/early_smbus.c</span><br><span>+++ b/src/northbridge/via/vx800/early_smbus.c</span><br><span>@@ -30,7 +30,7 @@</span><br><span> #define SMBBLKDAT SMBUS_IO_BASE + 0x7</span><br><span> #define SMBSLVCTL SMBUS_IO_BASE + 0x8</span><br><span> #define SMBTRNSADD SMBUS_IO_BASE + 0x9</span><br><span style="color: hsl(0, 100%, 40%);">-#define SMBSLVDATA SMBUS_IO_BASE + 0xa</span><br><span style="color: hsl(120, 100%, 40%);">+#define SMBSLVDATA SMBUS_IO_BASE + 0xa</span><br><span> #define SMLINK_PIN_CTL SMBUS_IO_BASE + 0xe</span><br><span> #define SMBUS_PIN_CTL SMBUS_IO_BASE + 0xf</span><br><span> </span><br><span>diff --git a/src/northbridge/via/vx800/uma_ram_setting.c b/src/northbridge/via/vx800/uma_ram_setting.c</span><br><span>index c9738da..8745979 100644</span><br><span>--- a/src/northbridge/via/vx800/uma_ram_setting.c</span><br><span>+++ b/src/northbridge/via/vx800/uma_ram_setting.c</span><br><span>@@ -24,7 +24,7 @@</span><br><span> #define UMARAM_512M 7</span><br><span> #define UMARAM_256M 6</span><br><span> #define UMARAM_128M 5</span><br><span style="color: hsl(0, 100%, 40%);">-#define UMARAM_64M 4</span><br><span style="color: hsl(120, 100%, 40%);">+#define UMARAM_64M 4</span><br><span> #define UMARAM_32M 3</span><br><span> #define UMARAM_16M 2</span><br><span> #define UMARAM_8M 1</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26603">change 26603</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935 </div>
<div style="display:none"> Gerrit-Change-Number: 26603 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Elyes HAOUAS <ehaouas@noos.fr> </div>