[coreboot-gerrit] Change in coreboot[master]: src/northbridge: Get rid of whitespace befor tab

Mon May 28 11:22:20 CEST 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/26603 )

Change subject: src/northbridge: Get rid of whitespace befor tab
......................................................................

Patch Set 1:

(20 comments)

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/agesa/family14/chip.h
File src/northbridge/amd/agesa/family14/chip.h:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/agesa/family14/chip.h@30
PS1, Line 30: 	 *	{ {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 (Unused)
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdht/h3gtopo.h
File src/northbridge/amd/amdht/h3gtopo.h:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdht/h3gtopo.h@259
PS1, Line 259: 	0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x00, 0x44, 0x10, 0xFF	// Node6
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/northbridge.c
File src/northbridge/amd/amdk8/northbridge.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/northbridge.c@982
PS1, Line 982: 					if (!is_cpu_pre_e0())
suspect code indent for conditional statements (40, 49)

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/northbridge.c@984
PS1, Line 984: 						 sizek += hoist_memory(mmio_basek,i);
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/northbridge.c@984
PS1, Line 984: 						 sizek += hoist_memory(mmio_basek,i);
space required after that ',' (ctx:VxV)

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/northbridge.c@1209
PS1, Line 1209: 					e0_later_single_core = is_e0_later_in_bsp(i);  // single core
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/northbridge.c@1211
PS1, Line 1211: 					e0_later_single_core = is_cpu_f0_in_bsp(i);  // We can read cpuid(1) from Func3
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/raminit.c
File src/northbridge/amd/amdk8/raminit.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdk8/raminit.c@1299
PS1, Line 1299: 	uint8_t	 rdpreamble[4]; /* 0 is for registered, 1 for 1-2 DIMMS, 2 and 3 for 3 or 4 unreg dimm slots */
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct/mct_d.c
File src/northbridge/amd/amdmct/mct/mct_d.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct/mct_d.c@3756
PS1, Line 3756: 	 *	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct/mctdqs_d.c
File src/northbridge/amd/amdmct/mct/mctdqs_d.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct/mctdqs_d.c@464
PS1, Line 464: 		BanksPresent = 1;	/* flag for at least one bank is present */
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
File src/northbridge/amd/amdmct/mct_ddr3/mct_d.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c@7912
PS1, Line 7912: 	 *	b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
File src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@118
PS1, Line 118: 	OB_ChipKill = mctGet_NVbits(NV_ChipKill);		/* ECC Chip-kill mode */
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c@123
PS1, Line 123: 		/* mct_AdjustScrub_D(pDCTstatA, &nvbits); */	/* Need not adjust */
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
File src/northbridge/amd/amdmct/mct_ddr3/s3utils.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c@699
PS1, Line 699: 			//	wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/lx/northbridgeinit.c
File src/northbridge/amd/lx/northbridgeinit.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/amd/lx/northbridgeinit.c@597
PS1, Line 597:  *  SYSRC(7:0) = 00h		 ; writeback, can set to 08h to make writethrough
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/cx700/early_smbus.c
File src/northbridge/via/cx700/early_smbus.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/cx700/early_smbus.c@30
PS1, Line 30: #define SMBSLVDATA		SMBUS_IO_BASE + 0xa
Macros with complex values should be enclosed in parentheses

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/cx700/raminit.c
File src/northbridge/via/cx700/raminit.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/cx700/raminit.c@211
PS1, Line 211: /*	RankMap, ODT Control Bits,							DRAM & NB ODT setting	*/
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/cx700/raminit.c@213
PS1, Line 213: 	0x03,	 ((NA_ODT << 6)    | (NA_ODT << 4)    | (Rank0_ODT << 2) | Rank1_ODT),	(DDR2_ODT_150ohm | NB_ODT_75ohm),
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/vx800/driving_setting.c
File src/northbridge/via/vx800/driving_setting.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/vx800/driving_setting.c@60
PS1, Line 60: 		So the register VIA_NB3DRAM_REGD4 and VIA_NB3DRAM_REGD3 should be
line over 80 characters

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/vx800/early_smbus.c
File src/northbridge/via/vx800/early_smbus.c:

https://review.coreboot.org/#/c/26603/1/src/northbridge/via/vx800/early_smbus.c@33
PS1, Line 33: #define SMBSLVDATA		SMBUS_IO_BASE + 0xa
Macros with complex values should be enclosed in parentheses

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Icf13c08129c71372e9870159bbe0a1b86af93935
Gerrit-Change-Number: 26603
Gerrit-PatchSet: 1
Gerrit-Owner: Elyes HAOUAS <ehaouas at noos.fr>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Mon, 28 May 2018 09:22:20 +0000
Gerrit-HasComments: Yes
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