[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Use common lockdown code
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Thu May 3 13:11:22 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/26032
Change subject: soc/intel/skylake: Use common lockdown code
......................................................................
soc/intel/skylake: Use common lockdown code
In previous patch, lockdown code has been added as part of common base
code and this code support is common across multiple SOCs. Skylake can
also use same common code instead of keeping redundant copy inside soc
folder. So removing lockdown.c from skylake folder and instead using
common lockdown code.
We need to implement soc specific function for skylake which returns soc
specific lockdown configuration to common code. This function has been
implemented inside chip.c and chip_fsp20.c files
BUG=none
BRANCH=none
TEST= code compiles with different configurations. No changes in code
logic.
Change-Id: I462ccf02424f6734cf6fb505eaf7ce6dcd2833d5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
D src/soc/intel/skylake/lockdown.c
5 files changed, 43 insertions(+), 114 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/26032/1
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 326b847..34b678d 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -55,6 +55,8 @@
select SMP
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
+ select SOC_INTEL_COMMON_BASECODE
+ select SOC_INTEL_COMMON_BASECODE_LOCKDOWN
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index ef95cf7..fc57274 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -50,7 +50,6 @@
ramstage-y += i2c.c
ramstage-y += graphics.c
ramstage-y += irq.c
-ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += me.c
ramstage-y += memmap.c
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 0c1dfa6..d91d611 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -20,6 +20,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <fsp/util.h>
+#include <intelbasecode/lockdown.h>
#include <intelblocks/xdci.h>
#include <soc/acpi.h>
#include <soc/interrupt.h>
@@ -832,3 +833,22 @@
original->FastPkgCRampDisable,
params->FastPkgCRampDisable);
}
+/*
+ * This function will return SOC specific lockdown configuration.
+ * Function can return 3 possible values:
+ * 1. -1 = device is NULL and we need to skip lockdown
+ * 2. 0 = CHIPSET_LOCKDOWN_FSP = Use FSP to lockdown IPs
+ * 3. 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown Ips
+ */
+int soc_get_lockdown_config(void)
+{
+ const struct soc_intel_skylake_config *config;
+ struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
+
+ if (dev == NULL || dev->chip_info == NULL)
+ return -1;
+
+ config = dev->chip_info;
+
+ return config->chipset_lockdown;
+}
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 6e91816..9236675 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -27,6 +27,7 @@
#include <device/pci.h>
#include <fsp/api.h>
#include <fsp/util.h>
+#include <intelbasecode/lockdown.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/acpi.h>
@@ -351,3 +352,23 @@
{
printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
}
+
+/*
+ * This function will return SOC specific lockdown configuration.
+ * Function can return 3 possible values:
+ * 1. -1 = device is NULL and we need to skip lockdown
+ * 2. 0 = CHIPSET_LOCKDOWN_FSP = Use FSP to lockdown IPs
+ * 3. 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown Ips
+ */
+int soc_get_lockdown_config(void)
+{
+ const struct soc_intel_skylake_config *config;
+ struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);
+
+ if (dev == NULL || dev->chip_info == NULL)
+ return -1;
+
+ config = dev->chip_info;
+
+ return config->chipset_lockdown;
+}
diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c
deleted file mode 100644
index 2331217..0000000
--- a/src/soc/intel/skylake/lockdown.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <bootstate.h>
-#include <chip.h>
-#include <intelblocks/fast_spi.h>
-#include <intelblocks/lpc_lib.h>
-#include <intelblocks/pcr.h>
-#include <soc/pci_devs.h>
-#include <soc/pcr_ids.h>
-#include <soc/pm.h>
-#include <string.h>
-
-#define PCR_DMI_GCS 0x274C
-#define PCR_DMI_GCS_BILD (1 << 0)
-
-static void lpc_lockdown_config(const struct soc_intel_skylake_config *config)
-{
- /* Set Bios Interface Lock, Bios Lock */
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
- lpc_set_bios_interface_lock_down();
- lpc_set_lock_enable();
- }
-}
-
-static void pmc_lockdown_config(void)
-{
- uint8_t *pmcbase;
- u32 pmsyncreg;
-
- /* PMSYNC */
- pmcbase = pmc_mmio_regs();
- pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);
- pmsyncreg |= PMSYNC_LOCK;
- write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);
-}
-
-static void dmi_lockdown_config(void)
-{
- /*
- * GCS reg of DMI
- *
- * When set, prevents GCS.BBS from being changed
- * GCS.BBS: (Boot BIOS Strap) This field determines the destination
- * of accesses to the BIOS memory range.
- * Bits Description
- * “0b”: SPI
- * “1b”: LPC/eSPI
- */
- pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);
-}
-
-static void spi_lockdown_config(const struct soc_intel_skylake_config *config)
-{
- /* Set FAST_SPI opcode menu */
- fast_spi_set_opcode_menu();
-
- /* Discrete Lock Flash PR registers */
- fast_spi_pr_dlock();
-
- /* Lock FAST_SPIBAR */
- fast_spi_lock_bar();
-
- /* Set Bios Interface Lock, Bios Lock */
- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
- /* Bios Interface Lock */
- fast_spi_set_bios_interface_lock_down();
-
- /* Bios Lock */
- fast_spi_set_lock_enable();
- }
-}
-
-static void platform_lockdown_config(void *unused)
-{
- struct soc_intel_skylake_config *config;
- struct device *dev;
-
- dev = PCH_DEV_SPI;
- /* Check if device is valid, else return */
- if (dev == NULL || dev->chip_info == NULL)
- return;
-
- config = dev->chip_info;
-
- /* LPC lock down configuration */
- lpc_lockdown_config(config);
-
- /* SPI lock down configuration */
- spi_lockdown_config(config);
-
- /* DMI lock down configuration */
- dmi_lockdown_config();
-
- /* PMC lock down configuration */
- pmc_lockdown_config();
-}
-
-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,
- NULL);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I462ccf02424f6734cf6fb505eaf7ce6dcd2833d5
Gerrit-Change-Number: 26032
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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