<p>Maulik V Vaghela has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/26032">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Use common lockdown code<br><br>In previous patch, lockdown code has been added as part of common base<br>code and this code support is common across multiple SOCs. Skylake can<br>also use same common code instead of keeping redundant copy inside soc<br>folder. So removing lockdown.c from skylake folder and instead using<br>common lockdown code.<br><br>We need to implement soc specific function for skylake which returns soc<br>specific lockdown configuration to common code. This function has been<br>implemented inside chip.c and chip_fsp20.c files<br><br>BUG=none<br>BRANCH=none<br>TEST= code compiles with different configurations. No changes in code<br>logic.<br><br>Change-Id: I462ccf02424f6734cf6fb505eaf7ce6dcd2833d5<br>Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com><br>---<br>M src/soc/intel/skylake/Kconfig<br>M src/soc/intel/skylake/Makefile.inc<br>M src/soc/intel/skylake/chip.c<br>M src/soc/intel/skylake/chip_fsp20.c<br>D src/soc/intel/skylake/lockdown.c<br>5 files changed, 43 insertions(+), 114 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/26032/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig</span><br><span>index 326b847..34b678d 100644</span><br><span>--- a/src/soc/intel/skylake/Kconfig</span><br><span>+++ b/src/soc/intel/skylake/Kconfig</span><br><span>@@ -55,6 +55,8 @@</span><br><span> select SMP</span><br><span> select SOC_INTEL_COMMON</span><br><span> select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE</span><br><span style="color: hsl(120, 100%, 40%);">+ select SOC_INTEL_COMMON_BASECODE_LOCKDOWN</span><br><span> select SOC_INTEL_COMMON_BLOCK</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU</span><br><span> select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT</span><br><span>diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc</span><br><span>index ef95cf7..fc57274 100644</span><br><span>--- a/src/soc/intel/skylake/Makefile.inc</span><br><span>+++ b/src/soc/intel/skylake/Makefile.inc</span><br><span>@@ -50,7 +50,6 @@</span><br><span> ramstage-y += i2c.c</span><br><span> ramstage-y += graphics.c</span><br><span> ramstage-y += irq.c</span><br><span style="color: hsl(0, 100%, 40%);">-ramstage-y += lockdown.c</span><br><span> ramstage-y += lpc.c</span><br><span> ramstage-y += me.c</span><br><span> ramstage-y += memmap.c</span><br><span>diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c</span><br><span>index 0c1dfa6..d91d611 100644</span><br><span>--- a/src/soc/intel/skylake/chip.c</span><br><span>+++ b/src/soc/intel/skylake/chip.c</span><br><span>@@ -20,6 +20,7 @@</span><br><span> #include <device/device.h></span><br><span> #include <device/pci.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/lockdown.h></span><br><span> #include <intelblocks/xdci.h></span><br><span> #include <soc/acpi.h></span><br><span> #include <soc/interrupt.h></span><br><span>@@ -832,3 +833,22 @@</span><br><span> original->FastPkgCRampDisable,</span><br><span> params->FastPkgCRampDisable);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function will return SOC specific lockdown configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Function can return 3 possible values:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1. -1 = device is NULL and we need to skip lockdown</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2. 0 = CHIPSET_LOCKDOWN_FSP = Use FSP to lockdown IPs</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3. 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown Ips</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int soc_get_lockdown_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_skylake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev == NULL || dev->chip_info == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return config->chipset_lockdown;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>index 6e91816..9236675 100644</span><br><span>--- a/src/soc/intel/skylake/chip_fsp20.c</span><br><span>+++ b/src/soc/intel/skylake/chip_fsp20.c</span><br><span>@@ -27,6 +27,7 @@</span><br><span> #include <device/pci.h></span><br><span> #include <fsp/api.h></span><br><span> #include <fsp/util.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <intelbasecode/lockdown.h></span><br><span> #include <intelblocks/xdci.h></span><br><span> #include <romstage_handoff.h></span><br><span> #include <soc/acpi.h></span><br><span>@@ -351,3 +352,23 @@</span><br><span> {</span><br><span> printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);</span><br><span> }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*</span><br><span style="color: hsl(120, 100%, 40%);">+ * This function will return SOC specific lockdown configuration.</span><br><span style="color: hsl(120, 100%, 40%);">+ * Function can return 3 possible values:</span><br><span style="color: hsl(120, 100%, 40%);">+ * 1. -1 = device is NULL and we need to skip lockdown</span><br><span style="color: hsl(120, 100%, 40%);">+ * 2. 0 = CHIPSET_LOCKDOWN_FSP = Use FSP to lockdown IPs</span><br><span style="color: hsl(120, 100%, 40%);">+ * 3. 1 = CHIPSET_LOCKDOWN_COREBOOT = Use coreboot to lockdown Ips</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+int soc_get_lockdown_config(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ const struct soc_intel_skylake_config *config;</span><br><span style="color: hsl(120, 100%, 40%);">+ struct device *dev = dev_find_slot(0, PCH_DEVFN_SPI);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (dev == NULL || dev->chip_info == NULL)</span><br><span style="color: hsl(120, 100%, 40%);">+ return -1;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ config = dev->chip_info;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ return config->chipset_lockdown;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span>diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c</span><br><span>deleted file mode 100644</span><br><span>index 2331217..0000000</span><br><span>--- a/src/soc/intel/skylake/lockdown.c</span><br><span>+++ /dev/null</span><br><span>@@ -1,113 +0,0 @@</span><br><span style="color: hsl(0, 100%, 40%);">-/*</span><br><span style="color: hsl(0, 100%, 40%);">- * This file is part of the coreboot project.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * Copyright (C) 2017 Intel Corporation.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is free software; you can redistribute it and/or modify</span><br><span style="color: hsl(0, 100%, 40%);">- * it under the terms of the GNU General Public License as published by</span><br><span style="color: hsl(0, 100%, 40%);">- * the Free Software Foundation; version 2 of the License.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * This program is distributed in the hope that it will be useful,</span><br><span style="color: hsl(0, 100%, 40%);">- * but WITHOUT ANY WARRANTY; without even the implied warranty of</span><br><span style="color: hsl(0, 100%, 40%);">- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the</span><br><span style="color: hsl(0, 100%, 40%);">- * GNU General Public License for more details.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#include <arch/io.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <bootstate.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <chip.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/fast_spi.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/lpc_lib.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <intelblocks/pcr.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pci_devs.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pcr_ids.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <soc/pm.h></span><br><span style="color: hsl(0, 100%, 40%);">-#include <string.h></span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_GCS 0x274C</span><br><span style="color: hsl(0, 100%, 40%);">-#define PCR_DMI_GCS_BILD (1 << 0)</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void lpc_lockdown_config(const struct soc_intel_skylake_config *config)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Bios Interface Lock, Bios Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_set_bios_interface_lock_down();</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_set_lock_enable();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void pmc_lockdown_config(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- uint8_t *pmcbase;</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pmsyncreg;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PMSYNC */</span><br><span style="color: hsl(0, 100%, 40%);">- pmcbase = pmc_mmio_regs();</span><br><span style="color: hsl(0, 100%, 40%);">- pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);</span><br><span style="color: hsl(0, 100%, 40%);">- pmsyncreg |= PMSYNC_LOCK;</span><br><span style="color: hsl(0, 100%, 40%);">- write32(pmcbase + PMSYNC_TPR_CFG, pmsyncreg);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void dmi_lockdown_config(void)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /*</span><br><span style="color: hsl(0, 100%, 40%);">- * GCS reg of DMI</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * When set, prevents GCS.BBS from being changed</span><br><span style="color: hsl(0, 100%, 40%);">- * GCS.BBS: (Boot BIOS Strap) This field determines the destination</span><br><span style="color: hsl(0, 100%, 40%);">- * of accesses to the BIOS memory range.</span><br><span style="color: hsl(0, 100%, 40%);">- * Bits Description</span><br><span style="color: hsl(0, 100%, 40%);">- * “0b”: SPI</span><br><span style="color: hsl(0, 100%, 40%);">- * “1b”: LPC/eSPI</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void spi_lockdown_config(const struct soc_intel_skylake_config *config)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set FAST_SPI opcode menu */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_set_opcode_menu();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Discrete Lock Flash PR registers */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_pr_dlock();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Lock FAST_SPIBAR */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_lock_bar();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Set Bios Interface Lock, Bios Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- if (config->chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bios Interface Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_set_bios_interface_lock_down();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Bios Lock */</span><br><span style="color: hsl(0, 100%, 40%);">- fast_spi_set_lock_enable();</span><br><span style="color: hsl(0, 100%, 40%);">- }</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-static void platform_lockdown_config(void *unused)</span><br><span style="color: hsl(0, 100%, 40%);">-{</span><br><span style="color: hsl(0, 100%, 40%);">- struct soc_intel_skylake_config *config;</span><br><span style="color: hsl(0, 100%, 40%);">- struct device *dev;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- dev = PCH_DEV_SPI;</span><br><span style="color: hsl(0, 100%, 40%);">- /* Check if device is valid, else return */</span><br><span style="color: hsl(0, 100%, 40%);">- if (dev == NULL || dev->chip_info == NULL)</span><br><span style="color: hsl(0, 100%, 40%);">- return;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- config = dev->chip_info;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* LPC lock down configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- lpc_lockdown_config(config);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* SPI lock down configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- spi_lockdown_config(config);</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* DMI lock down configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- dmi_lockdown_config();</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* PMC lock down configuration */</span><br><span style="color: hsl(0, 100%, 40%);">- pmc_lockdown_config();</span><br><span style="color: hsl(0, 100%, 40%);">-}</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">-BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,</span><br><span style="color: hsl(0, 100%, 40%);">- NULL);</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/26032">change 26032</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I462ccf02424f6734cf6fb505eaf7ce6dcd2833d5 </div>
<div style="display:none"> Gerrit-Change-Number: 26032 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela@intel.com> </div>