[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[Julien Viard de Galbert (Code Review)]

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/25442


Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
......................................................................

soc/intel/denverton_ns: Implement PCIe post config + lock

Configure PCIe maximum payload size to fix Intel SSD
Lock Down PCIe Configuration

Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert at online.net>
---
M src/soc/intel/denverton_ns/lpc.c
1 file changed, 35 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/1

diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index 8f2542a..f52bbfe 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -378,12 +378,47 @@
 
 }
 
+static void spi_lock_pcie(void)
+{
+	int i;
+	struct device *dev;
+	uint16_t reg16;
+	for (i = 0; i < MAX_PCIE_PORT; i++) {
+		if (i < 4)
+			dev = dev_find_slot(0, PCI_DEVFN(PCIE_PORT1_DEV + i,
+					    PCIE_PORT1_FUNC));
+		else
+			dev = dev_find_slot(0, PCI_DEVFN(PCIE_PORT2_DEV + i,
+					    PCIE_PORT1_FUNC));
+
+		if (dev == NULL) {
+			printk(BIOS_DEBUG, "PCIe Port%d NOT AVAILABLE!\n", i);
+			continue;
+		}
+
+		reg16 = pci_read_config16(dev, 0x48);
+		printk(BIOS_DEBUG, "PCIe Port%d DEVCTL:0x%x\n", i, reg16);
+		/* Set MRRS & MPS to 128 bytes */
+		reg16 &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_PAYLOAD);
+		pci_write_config16(dev, 0x48, reg16);
+
+		reg16 = pci_read_config16(dev, 0xEA);
+		printk(BIOS_DEBUG, "PCIe Port%d PLKCTL:0x%x\n", i, reg16);
+		reg16 |= 7; /* Lock bits */
+		pci_write_config16(dev, 0xEA, reg16);
+	}
+
+}
+
 static void finalize_chipset(void *unused)
 {
 	bool relax_security = fsp_relax_security();
 
 	spi_lock_bar(relax_security);
 
+	if(!relax_security)
+		spi_lock_pcie();
+
 	printk(BIOS_DEBUG, "Finalizing SMM.\n");
 	outb(APM_CNT_FINALIZE, APM_CNT);
 }

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert at online.net>
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