[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25442 )

Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock
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Patch Set 1: Verified-1

Build Failed 

https://qa.coreboot.org/job/coreboot-gerrit/69215/ : FAILURE

https://qa.coreboot.org/job/coreboot-checkpatch/23564/ : SUCCESS


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd
Gerrit-Change-Number: 25442
Gerrit-PatchSet: 1
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert at online.net>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 29 Mar 2018 13:33:32 +0000
Gerrit-HasComments: No
Gerrit-HasLabels: Yes
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