<p>Julien Viard de Galbert has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/25442">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/denverton_ns: Implement PCIe post config + lock<br><br>Configure PCIe maximum payload size to fix Intel SSD<br>Lock Down PCIe Configuration<br><br>Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd<br>Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net><br>---<br>M src/soc/intel/denverton_ns/lpc.c<br>1 file changed, 35 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c</span><br><span>index 8f2542a..f52bbfe 100644</span><br><span>--- a/src/soc/intel/denverton_ns/lpc.c</span><br><span>+++ b/src/soc/intel/denverton_ns/lpc.c</span><br><span>@@ -378,12 +378,47 @@</span><br><span> </span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void spi_lock_pcie(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+   int i;</span><br><span style="color: hsl(120, 100%, 40%);">+        struct device *dev;</span><br><span style="color: hsl(120, 100%, 40%);">+   uint16_t reg16;</span><br><span style="color: hsl(120, 100%, 40%);">+       for (i = 0; i < MAX_PCIE_PORT; i++) {</span><br><span style="color: hsl(120, 100%, 40%);">+              if (i < 4)</span><br><span style="color: hsl(120, 100%, 40%);">+                 dev = dev_find_slot(0, PCI_DEVFN(PCIE_PORT1_DEV + i,</span><br><span style="color: hsl(120, 100%, 40%);">+                                      PCIE_PORT1_FUNC));</span><br><span style="color: hsl(120, 100%, 40%);">+                else</span><br><span style="color: hsl(120, 100%, 40%);">+                  dev = dev_find_slot(0, PCI_DEVFN(PCIE_PORT2_DEV + i,</span><br><span style="color: hsl(120, 100%, 40%);">+                                      PCIE_PORT1_FUNC));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+              if (dev == NULL) {</span><br><span style="color: hsl(120, 100%, 40%);">+                    printk(BIOS_DEBUG, "PCIe Port%d NOT AVAILABLE!\n", i);</span><br><span style="color: hsl(120, 100%, 40%);">+                      continue;</span><br><span style="color: hsl(120, 100%, 40%);">+             }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+           reg16 = pci_read_config16(dev, 0x48);</span><br><span style="color: hsl(120, 100%, 40%);">+         printk(BIOS_DEBUG, "PCIe Port%d DEVCTL:0x%x\n", i, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+          /* Set MRRS & MPS to 128 bytes */</span><br><span style="color: hsl(120, 100%, 40%);">+         reg16 &= ~(PCI_EXP_DEVCTL_READRQ | PCI_EXP_DEVCTL_PAYLOAD);</span><br><span style="color: hsl(120, 100%, 40%);">+               pci_write_config16(dev, 0x48, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+               reg16 = pci_read_config16(dev, 0xEA);</span><br><span style="color: hsl(120, 100%, 40%);">+         printk(BIOS_DEBUG, "PCIe Port%d PLKCTL:0x%x\n", i, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+          reg16 |= 7; /* Lock bits */</span><br><span style="color: hsl(120, 100%, 40%);">+           pci_write_config16(dev, 0xEA, reg16);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static void finalize_chipset(void *unused)</span><br><span> {</span><br><span>  bool relax_security = fsp_relax_security();</span><br><span> </span><br><span>      spi_lock_bar(relax_security);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+     if(!relax_security)</span><br><span style="color: hsl(120, 100%, 40%);">+           spi_lock_pcie();</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span>   printk(BIOS_DEBUG, "Finalizing SMM.\n");</span><br><span>   outb(APM_CNT_FINALIZE, APM_CNT);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/25442">change 25442</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/25442"/><meta itemprop="name" content="View Change"/><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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd </div>
<div style="display:none"> Gerrit-Change-Number: 25442 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert@online.net> </div>