[coreboot-gerrit] Change in coreboot[master]: sb/intel/common/smihandler: Use new PMBASE API
Patrick Rudolph (Code Review)
gerrit at coreboot.org
Fri Jun 29 10:46:29 CEST 2018
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27281
Change subject: sb/intel/common/smihandler: Use new PMBASE API
......................................................................
sb/intel/common/smihandler: Use new PMBASE API
Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97
Signed-off-by: Patrick Rudolph <patrick.rudolph at 9elements.com>
---
M src/southbridge/intel/common/smihandler.c
1 file changed, 15 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27281/1
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index a5ebf25..5cdc992 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -30,8 +30,6 @@
static int smm_initialized = 0;
-static u16 pmbase;
-
void gpi_route_interrupt(u8 gpi, u8 mode)
{
u32 gpi_rout;
@@ -57,11 +55,7 @@
*/
void southbridge_smi_set_eos(void)
{
- u8 reg8;
-
- reg8 = inb(pmbase + SMI_EN);
- reg8 |= EOS;
- outb(reg8, pmbase + SMI_EN);
+ write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) | EOS);
}
static void busmaster_disable_on_bus(int bus)
@@ -124,12 +118,10 @@
outb(tmp72, 0x72);
/* First, disable further SMIs */
- reg8 = inb(pmbase + SMI_EN);
- reg8 &= ~SLP_SMI_EN;
- outb(reg8, pmbase + SMI_EN);
+ write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN);
/* Figure out SLP_TYP */
- reg32 = inl(pmbase + PM1_CNT);
+ reg32 = read_pmbase32(PM1_CNT);
printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
slp_typ = acpi_sleep_from_pm1(reg32);
@@ -169,7 +161,7 @@
case ACPI_S5:
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
- outl(0, pmbase + GPE0_EN);
+ write_pmbase32(GPE0_EN, 0);
/* Always set the flag in case CMOS was changed on runtime. For
* "KEEP", switch to "OFF" - KEEP is software emulated
@@ -192,7 +184,7 @@
* event again. We need to set BIT13 (SLP_EN) though to make the
* sleep happen.
*/
- outl(reg32 | SLP_EN, pmbase + PM1_CNT);
+ write_pmbase32(PM1_CNT, reg32 | SLP_EN);
/* Make sure to stop executing code here for S3/S4/S5 */
if (slp_typ >= ACPI_S3)
@@ -202,11 +194,11 @@
* the line above. However, if we entered sleep state S1 and wake
* up again, we will continue to execute code in this function.
*/
- reg32 = inl(pmbase + PM1_CNT);
+ reg32 = read_pmbase32(PM1_CNT);
if (reg32 & SCI_EN) {
/* The OS is not an ACPI OS, so we set the state to S0 */
reg32 &= ~(SLP_EN | SLP_TYP);
- outl(reg32, pmbase + PM1_CNT);
+ write_pmbase32(PM1_CNT, reg32);
}
}
@@ -273,7 +265,6 @@
static void southbridge_smi_apmc(void)
{
- u32 pmctrl;
u8 reg8;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -295,15 +286,11 @@
printk(BIOS_DEBUG, "P-state control\n");
break;
case APM_CNT_ACPI_DISABLE:
- pmctrl = inl(pmbase + PM1_CNT);
- pmctrl &= ~SCI_EN;
- outl(pmctrl, pmbase + PM1_CNT);
+ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) &~SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
break;
case APM_CNT_ACPI_ENABLE:
- pmctrl = inl(pmbase + PM1_CNT);
- pmctrl |= SCI_EN;
- outl(pmctrl, pmbase + PM1_CNT);
+ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN);
printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
break;
case APM_CNT_GNVS_UPDATE:
@@ -350,7 +337,7 @@
#if IS_ENABLED(CONFIG_ELOG_GSMI)
elog_add_event(ELOG_TYPE_POWER_BUTTON);
#endif
- outl(reg32, pmbase + PM1_CNT);
+ write_pmbase32(PM1_CNT, reg32);
}
}
@@ -365,24 +352,23 @@
static void southbridge_smi_gpi(void)
{
u16 reg16;
- reg16 = inw(pmbase + ALT_GP_SMI_STS);
- outw(reg16, pmbase + ALT_GP_SMI_STS);
- reg16 &= inw(pmbase + ALT_GP_SMI_EN);
+ reg16 = reset_alt_gp_smi_status();
+ reg16 &= read_pmbase16(ALT_GP_SMI_EN);
mainboard_smi_gpi(reg16);
if (reg16)
printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);
- outw(reg16, pmbase + ALT_GP_SMI_STS);
+ write_pmbase16(ALT_GP_SMI_STS, reg16);
}
static void southbridge_smi_mc(void)
{
u32 reg32;
- reg32 = inl(pmbase + SMI_EN);
+ reg32 = read_pmbase32(SMI_EN);
/* Are periodic SMIs enabled? */
if ((reg32 & MCSMI_EN) == 0)
@@ -435,7 +421,7 @@
{
u32 reg32;
- reg32 = inl(pmbase + SMI_EN);
+ reg32 = read_pmbase32(SMI_EN);
/* Are periodic SMIs enabled? */
if ((reg32 & PERIODIC_EN) == 0)
@@ -491,9 +477,6 @@
int i, dump = 0;
u32 smi_sts;
- /* Update global variable pmbase */
- pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
-
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
--
To view, visit https://review.coreboot.org/27281
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97
Gerrit-Change-Number: 27281
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <patrick.rudolph at 9elements.com>
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