<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27281">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/common/smihandler: Use new PMBASE API<br><br>Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97<br>Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com><br>---<br>M src/southbridge/intel/common/smihandler.c<br>1 file changed, 15 insertions(+), 32 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/27281/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c</span><br><span>index a5ebf25..5cdc992 100644</span><br><span>--- a/src/southbridge/intel/common/smihandler.c</span><br><span>+++ b/src/southbridge/intel/common/smihandler.c</span><br><span>@@ -30,8 +30,6 @@</span><br><span> </span><br><span> static int smm_initialized = 0;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-static u16 pmbase;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> void gpi_route_interrupt(u8 gpi, u8 mode)</span><br><span> {</span><br><span> u32 gpi_rout;</span><br><span>@@ -57,11 +55,7 @@</span><br><span> */</span><br><span> void southbridge_smi_set_eos(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 reg8;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 |= EOS;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) | EOS);</span><br><span> }</span><br><span> </span><br><span> static void busmaster_disable_on_bus(int bus)</span><br><span>@@ -124,12 +118,10 @@</span><br><span> outb(tmp72, 0x72);</span><br><span> </span><br><span> /* First, disable further SMIs */</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 = inb(pmbase + SMI_EN);</span><br><span style="color: hsl(0, 100%, 40%);">- reg8 &= ~SLP_SMI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outb(reg8, pmbase + SMI_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase8(SMI_EN, read_pmbase8(SMI_EN) & ~SLP_SMI_EN);</span><br><span> </span><br><span> /* Figure out SLP_TYP */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read_pmbase32(PM1_CNT);</span><br><span> printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);</span><br><span> slp_typ = acpi_sleep_from_pm1(reg32);</span><br><span> </span><br><span>@@ -169,7 +161,7 @@</span><br><span> case ACPI_S5:</span><br><span> printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- outl(0, pmbase + GPE0_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase32(GPE0_EN, 0);</span><br><span> </span><br><span> /* Always set the flag in case CMOS was changed on runtime. For</span><br><span> * "KEEP", switch to "OFF" - KEEP is software emulated</span><br><span>@@ -192,7 +184,7 @@</span><br><span> * event again. We need to set BIT13 (SLP_EN) though to make the</span><br><span> * sleep happen.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32 | SLP_EN, pmbase + PM1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase32(PM1_CNT, reg32 | SLP_EN);</span><br><span> </span><br><span> /* Make sure to stop executing code here for S3/S4/S5 */</span><br><span> if (slp_typ >= ACPI_S3)</span><br><span>@@ -202,11 +194,11 @@</span><br><span> * the line above. However, if we entered sleep state S1 and wake</span><br><span> * up again, we will continue to execute code in this function.</span><br><span> */</span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read_pmbase32(PM1_CNT);</span><br><span> if (reg32 & SCI_EN) {</span><br><span> /* The OS is not an ACPI OS, so we set the state to S0 */</span><br><span> reg32 &= ~(SLP_EN | SLP_TYP);</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + PM1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase32(PM1_CNT, reg32);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -273,7 +265,6 @@</span><br><span> </span><br><span> static void southbridge_smi_apmc(void)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u32 pmctrl;</span><br><span> u8 reg8;</span><br><span> </span><br><span> /* Emulate B2 register as the FADT / Linux expects it */</span><br><span>@@ -295,15 +286,11 @@</span><br><span> printk(BIOS_DEBUG, "P-state control\n");</span><br><span> break;</span><br><span> case APM_CNT_ACPI_DISABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl &= ~SCI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(pmctrl, pmbase + PM1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) &~SCI_EN);</span><br><span> printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");</span><br><span> break;</span><br><span> case APM_CNT_ACPI_ENABLE:</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl = inl(pmbase + PM1_CNT);</span><br><span style="color: hsl(0, 100%, 40%);">- pmctrl |= SCI_EN;</span><br><span style="color: hsl(0, 100%, 40%);">- outl(pmctrl, pmbase + PM1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) | SCI_EN);</span><br><span> printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");</span><br><span> break;</span><br><span> case APM_CNT_GNVS_UPDATE:</span><br><span>@@ -350,7 +337,7 @@</span><br><span> #if IS_ENABLED(CONFIG_ELOG_GSMI)</span><br><span> elog_add_event(ELOG_TYPE_POWER_BUTTON);</span><br><span> #endif</span><br><span style="color: hsl(0, 100%, 40%);">- outl(reg32, pmbase + PM1_CNT);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase32(PM1_CNT, reg32);</span><br><span> }</span><br><span> }</span><br><span> </span><br><span>@@ -365,24 +352,23 @@</span><br><span> static void southbridge_smi_gpi(void)</span><br><span> {</span><br><span> u16 reg16;</span><br><span style="color: hsl(0, 100%, 40%);">- reg16 = inw(pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg16 &= inw(pmbase + ALT_GP_SMI_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 = reset_alt_gp_smi_status();</span><br><span style="color: hsl(120, 100%, 40%);">+ reg16 &= read_pmbase16(ALT_GP_SMI_EN);</span><br><span> </span><br><span> mainboard_smi_gpi(reg16);</span><br><span> </span><br><span> if (reg16)</span><br><span> printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- outw(reg16, pmbase + ALT_GP_SMI_STS);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_pmbase16(ALT_GP_SMI_STS, reg16);</span><br><span> }</span><br><span> </span><br><span> static void southbridge_smi_mc(void)</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read_pmbase32(SMI_EN);</span><br><span> </span><br><span> /* Are periodic SMIs enabled? */</span><br><span> if ((reg32 & MCSMI_EN) == 0)</span><br><span>@@ -435,7 +421,7 @@</span><br><span> {</span><br><span> u32 reg32;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- reg32 = inl(pmbase + SMI_EN);</span><br><span style="color: hsl(120, 100%, 40%);">+ reg32 = read_pmbase32(SMI_EN);</span><br><span> </span><br><span> /* Are periodic SMIs enabled? */</span><br><span> if ((reg32 & PERIODIC_EN) == 0)</span><br><span>@@ -491,9 +477,6 @@</span><br><span> int i, dump = 0;</span><br><span> u32 smi_sts;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Update global variable pmbase */</span><br><span style="color: hsl(0, 100%, 40%);">- pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span> /* We need to clear the SMI status registers, or we won't see what's</span><br><span> * happening in the following calls.</span><br><span> */</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27281">change 27281</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4c64233ecdb8c1e28b319d84149f34bc8f1e4b97 </div>
<div style="display:none"> Gerrit-Change-Number: 27281 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <patrick.rudolph@9elements.com> </div>