[coreboot-gerrit] Change in coreboot[master]: inteltool: Add PCI IDs for the C220 PCH series
Quan Tran (Code Review)
gerrit at coreboot.org
Wed Jun 20 01:59:48 CEST 2018
Quan Tran has uploaded this change for review. ( https://review.coreboot.org/27168
Change subject: inteltool: Add PCI IDs for the C220 PCH series
......................................................................
inteltool: Add PCI IDs for the C220 PCH series
The C220 PCH series is a ICH8 generation southbridge. There is already existing code
to dump this southbridge. This patch adds the missing PCI IDs to
allow the tool to dump them.
Documentation on the PCH can be found here:
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/8-series-chipset-pch-datasheet.pdf
Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Signed-off-by: Quan Tran <qeed.quan at gmail.com>
---
M util/inteltool/gpio.c
M util/inteltool/inteltool.c
M util/inteltool/inteltool.h
M util/inteltool/powermgt.c
M util/inteltool/rootcmplx.c
M util/inteltool/spi.c
6 files changed, 121 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/27168/1
diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c
index 5e31035..5ef96fd 100644
--- a/util/inteltool/gpio.c
+++ b/util/inteltool/gpio.c
@@ -849,6 +849,21 @@
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ case PCI_DEVICE_ID_INTEL_C8_MOBILE:
+ case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
+ case PCI_DEVICE_ID_INTEL_Z87:
+ case PCI_DEVICE_ID_INTEL_Z85:
+ case PCI_DEVICE_ID_INTEL_HM86:
+ case PCI_DEVICE_ID_INTEL_H87:
+ case PCI_DEVICE_ID_INTEL_HM87:
+ case PCI_DEVICE_ID_INTEL_Q85:
+ case PCI_DEVICE_ID_INTEL_Q87:
+ case PCI_DEVICE_ID_INTEL_QM87:
+ case PCI_DEVICE_ID_INTEL_B85:
+ case PCI_DEVICE_ID_INTEL_C222:
+ case PCI_DEVICE_ID_INTEL_C224:
+ case PCI_DEVICE_ID_INTEL_C226:
+ case PCI_DEVICE_ID_INTEL_H81:
gpiobase = pci_read_word(sb, 0x48) & 0xfffc;
gpio_registers = lynxpoint_lp_gpio_registers;
size = ARRAY_SIZE(lynxpoint_lp_gpio_registers);
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index 24d62e1..e475157 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -232,6 +232,36 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_MOBILE,
+ "Intel(R) C8 Mobile"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C8_DESKTOP,
+ "Intel(R) C8 Desktop"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z87,
+ "Intel(R) Z87"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z85,
+ "Intel(R) Z85"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM86,
+ "Intel(R) HM86"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H87,
+ "Intel(R) H87"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM87,
+ "Intel(R) HM87"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q85,
+ "Intel(R) Q85"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q87,
+ "Intel(R) Q87"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM87,
+ "Intel(R) QM87"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_B85,
+ "Intel(R) B85"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C222,
+ "Intel(R) C222"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C224,
+ "Intel(R) C224"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_C226,
+ "Intel(R) C226"},
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H81,
+ "Intel(R) H81"},
/* Intel GPUs */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_G35_EXPRESS,
"Intel(R) G35 Express Chipset Family" },
diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h
index 3ca91cd..7f2372b 100644
--- a/util/inteltool/inteltool.h
+++ b/util/inteltool/inteltool.h
@@ -184,6 +184,22 @@
#define PCI_DEVICE_ID_INTEL_82B43 0x2e40
#define PCI_DEVICE_ID_INTEL_82B43_2 0x2e90
+#define PCI_DEVICE_ID_INTEL_C8_MOBILE 0x8c41
+#define PCI_DEVICE_ID_INTEL_C8_DESKTOP 0x8c42
+#define PCI_DEVICE_ID_INTEL_Z87 0x8c44
+#define PCI_DEVICE_ID_INTEL_Z85 0x8c46
+#define PCI_DEVICE_ID_INTEL_HM86 0x8c49
+#define PCI_DEVICE_ID_INTEL_H87 0x8c4a
+#define PCI_DEVICE_ID_INTEL_HM87 0x8c4b
+#define PCI_DEVICE_ID_INTEL_Q85 0x8c4c
+#define PCI_DEVICE_ID_INTEL_Q87 0x8c4e
+#define PCI_DEVICE_ID_INTEL_QM87 0x8c4f
+#define PCI_DEVICE_ID_INTEL_B85 0x8c50
+#define PCI_DEVICE_ID_INTEL_C222 0x8c52
+#define PCI_DEVICE_ID_INTEL_C224 0x8c54
+#define PCI_DEVICE_ID_INTEL_C226 0x8c56
+#define PCI_DEVICE_ID_INTEL_H81 0x8c5c
+
#define PCI_DEVICE_ID_INTEL_82X58 0x3405
#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index f022904..45cbb33 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -730,6 +730,21 @@
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
case PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC:
+ case PCI_DEVICE_ID_INTEL_C8_MOBILE:
+ case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
+ case PCI_DEVICE_ID_INTEL_Z87:
+ case PCI_DEVICE_ID_INTEL_Z85:
+ case PCI_DEVICE_ID_INTEL_HM86:
+ case PCI_DEVICE_ID_INTEL_H87:
+ case PCI_DEVICE_ID_INTEL_HM87:
+ case PCI_DEVICE_ID_INTEL_Q85:
+ case PCI_DEVICE_ID_INTEL_Q87:
+ case PCI_DEVICE_ID_INTEL_QM87:
+ case PCI_DEVICE_ID_INTEL_B85:
+ case PCI_DEVICE_ID_INTEL_C222:
+ case PCI_DEVICE_ID_INTEL_C224:
+ case PCI_DEVICE_ID_INTEL_C226:
+ case PCI_DEVICE_ID_INTEL_H81:
pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = pch_pm_registers;
size = ARRAY_SIZE(pch_pm_registers);
diff --git a/util/inteltool/rootcmplx.c b/util/inteltool/rootcmplx.c
index 2ad3410..76cb287 100644
--- a/util/inteltool/rootcmplx.c
+++ b/util/inteltool/rootcmplx.c
@@ -97,6 +97,21 @@
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ case PCI_DEVICE_ID_INTEL_C8_MOBILE:
+ case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
+ case PCI_DEVICE_ID_INTEL_Z87:
+ case PCI_DEVICE_ID_INTEL_Z85:
+ case PCI_DEVICE_ID_INTEL_HM86:
+ case PCI_DEVICE_ID_INTEL_H87:
+ case PCI_DEVICE_ID_INTEL_HM87:
+ case PCI_DEVICE_ID_INTEL_Q85:
+ case PCI_DEVICE_ID_INTEL_Q87:
+ case PCI_DEVICE_ID_INTEL_QM87:
+ case PCI_DEVICE_ID_INTEL_B85:
+ case PCI_DEVICE_ID_INTEL_C222:
+ case PCI_DEVICE_ID_INTEL_C224:
+ case PCI_DEVICE_ID_INTEL_C226:
+ case PCI_DEVICE_ID_INTEL_H81:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break;
case PCI_DEVICE_ID_INTEL_ICH:
diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c
index 6d11fa5..18600b6 100644
--- a/util/inteltool/spi.c
+++ b/util/inteltool/spi.c
@@ -160,6 +160,21 @@
case PCI_DEVICE_ID_INTEL_HM75:
case PCI_DEVICE_ID_INTEL_HM70:
case PCI_DEVICE_ID_INTEL_NM70:
+ case PCI_DEVICE_ID_INTEL_C8_MOBILE:
+ case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
+ case PCI_DEVICE_ID_INTEL_Z87:
+ case PCI_DEVICE_ID_INTEL_Z85:
+ case PCI_DEVICE_ID_INTEL_HM86:
+ case PCI_DEVICE_ID_INTEL_H87:
+ case PCI_DEVICE_ID_INTEL_HM87:
+ case PCI_DEVICE_ID_INTEL_Q85:
+ case PCI_DEVICE_ID_INTEL_Q87:
+ case PCI_DEVICE_ID_INTEL_QM87:
+ case PCI_DEVICE_ID_INTEL_B85:
+ case PCI_DEVICE_ID_INTEL_C222:
+ case PCI_DEVICE_ID_INTEL_C224:
+ case PCI_DEVICE_ID_INTEL_C226:
+ case PCI_DEVICE_ID_INTEL_H81:
bios_cntl = pci_read_byte(sb, 0xdc);
bios_cntl_register = pch_bios_cntl_registers;
size = ARRAY_SIZE(pch_bios_cntl_registers);
@@ -273,6 +288,21 @@
case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM:
case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
+ case PCI_DEVICE_ID_INTEL_C8_MOBILE:
+ case PCI_DEVICE_ID_INTEL_C8_DESKTOP:
+ case PCI_DEVICE_ID_INTEL_Z87:
+ case PCI_DEVICE_ID_INTEL_Z85:
+ case PCI_DEVICE_ID_INTEL_HM86:
+ case PCI_DEVICE_ID_INTEL_H87:
+ case PCI_DEVICE_ID_INTEL_HM87:
+ case PCI_DEVICE_ID_INTEL_Q85:
+ case PCI_DEVICE_ID_INTEL_Q87:
+ case PCI_DEVICE_ID_INTEL_QM87:
+ case PCI_DEVICE_ID_INTEL_B85:
+ case PCI_DEVICE_ID_INTEL_C222:
+ case PCI_DEVICE_ID_INTEL_C224:
+ case PCI_DEVICE_ID_INTEL_C226:
+ case PCI_DEVICE_ID_INTEL_H81:
spibaroffset = ICH9_SPIBAR;
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
size = ARRAY_SIZE(spi_bar_registers);
--
To view, visit https://review.coreboot.org/27168
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I07a8f2e9cb0ee8677c8fe2c51881147ed81c1a35
Gerrit-Change-Number: 27168
Gerrit-PatchSet: 1
Gerrit-Owner: Quan Tran <qeed.quan at gmail.com>
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