[coreboot-gerrit] Change in coreboot[master]: mb/pcengines/alix/romstage.c: clean up the transition to RAM
Michał Żygowski (Code Review)
gerrit at coreboot.org
Tue Jul 31 13:59:34 CEST 2018
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/27749
Change subject: mb/pcengines/alix/romstage.c: clean up the transition to RAM
......................................................................
mb/pcengines/alix/romstage.c: clean up the transition to RAM
Clean up the code which implied that return does not work in
mainboard_romstage_entry. Doing a wbinvd when CR0 NW and CD bits
are set caused the loss of return adress from the function, because
it behaved like invd. Remove redundant stack self-copying code
and invalidate cache in cache_as_ram.inc as it is sufficient to
switch to RAM.
Change-Id: I21f2341091d49d105026a12022c52d811d71feeb
Signed-off-by: Michał Żygowski <michal.zygowski at 3mdeb.com>
---
M src/cpu/amd/geode_lx/cache_as_ram.inc
M src/mainboard/pcengines/alix1c/romstage.c
M src/mainboard/pcengines/alix2d/romstage.c
3 files changed, 4 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27749/1
diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc
index 8250d72..1569cc3 100644
--- a/src/cpu/amd/geode_lx/cache_as_ram.inc
+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc
@@ -183,25 +183,11 @@
/* Call romstage.c main function */
call mainboard_romstage_entry
-.global done_cache_as_ram_main
-done_cache_as_ram_main:
+ /* Switch from Cache as RAM to real RAM. */
+ /* Invalidate the cache since there is nothing on the stack */
+ /* Then re-enable the cache */
+ invd
- /* We now run over the stack-in-cache,
- * copying it back to itself to invalidate the cache */
-
- push %edi
- mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
- push %esi
- mov $(CONFIG_DCACHE_RAM_BASE),%edi
- mov %edi,%esi
- cld
- rep movsl %ds:(%esi),%es:(%edi)
- pop %esi
- pop %edi
-
- /* Clear the cache out to RAM */
- wbinvd
- /* re-enable the cache */
movl %cr0, %eax
xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
movl %eax, %cr0
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index 8fe2dc0..e59873f 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -115,35 +115,5 @@
sdram_initialize(1, memctrl);
- /* Switch from Cache as RAM to real RAM.
- *
- * There are two ways we could think about this.
- *
- * 1. If we are using the romstage.inc ROMCC way, the stack is
- * going to be re-setup in the code following this code. Just
- * wbinvd the stack to clear the cache tags. We don't care
- * where the stack used to be.
- *
- * 2. This file is built as a normal .c -> .o and linked in
- * etc. The stack might be used to return etc. That means we
- * care about what is in the stack. If we are smart we set
- * the CAR stack to the same location as the rest of
- * coreboot. If that is the case we can just do a wbinvd.
- * The stack will be written into real RAM that is now setup
- * and we continue like nothing happened. If the stack is
- * located somewhere other than where LB would like it, you
- * need to write some code to do a copy from cache to RAM
- *
- * We use method 1 on Norwich and on this board too.
- */
post_code(0x02);
- printk(BIOS_ERR, "POST 02\n");
- __asm__("wbinvd\n");
- printk(BIOS_ERR, "Past wbinvd\n");
-
- /* We are finding the return does not work on this board. Explicitly
- * call the label that is after the call to us. This is gross, but
- * sometimes at this level it is the only way out.
- */
- done_cache_as_ram_main();
}
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index da3913d..b05140c 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -138,35 +138,5 @@
sdram_initialize(1, memctrl);
- /* Switch from Cache as RAM to real RAM.
- *
- * There are two ways we could think about this.
- *
- * 1. If we are using the romstage.inc ROMCC way, the stack is
- * going to be re-setup in the code following this code. Just
- * wbinvd the stack to clear the cache tags. We don't care
- * where the stack used to be.
- *
- * 2. This file is built as a normal .c -> .o and linked in
- * etc. The stack might be used to return etc. That means we
- * care about what is in the stack. If we are smart we set
- * the CAR stack to the same location as the rest of
- * coreboot. If that is the case we can just do a wbinvd.
- * The stack will be written into real RAM that is now setup
- * and we continue like nothing happened. If the stack is
- * located somewhere other than where LB would like it, you
- * need to write some code to do a copy from cache to RAM
- *
- * We use method 1 on Norwich and on this board too.
- */
post_code(0x02);
- printk(BIOS_ERR, "POST 02\n");
- __asm__("wbinvd\n");
- printk(BIOS_ERR, "Past wbinvd\n");
-
- /* We are finding the return does not work on this board. Explicitly
- * call the label that is after the call to us. This is gross, but
- * sometimes at this level it is the only way out.
- */
- done_cache_as_ram_main();
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I21f2341091d49d105026a12022c52d811d71feeb
Gerrit-Change-Number: 27749
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski at 3mdeb.com>
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