<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27749">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/pcengines/alix/romstage.c: clean up the transition to RAM<br><br>Clean up the code which implied that return does not work in<br>mainboard_romstage_entry. Doing a wbinvd when CR0 NW and CD bits<br>are set caused the loss of return adress from the function, because<br>it behaved like invd. Remove redundant stack self-copying code<br>and invalidate cache in cache_as_ram.inc as it is sufficient to<br>switch to RAM.<br><br>Change-Id: I21f2341091d49d105026a12022c52d811d71feeb<br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>---<br>M src/cpu/amd/geode_lx/cache_as_ram.inc<br>M src/mainboard/pcengines/alix1c/romstage.c<br>M src/mainboard/pcengines/alix2d/romstage.c<br>3 files changed, 4 insertions(+), 78 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/27749/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/amd/geode_lx/cache_as_ram.inc b/src/cpu/amd/geode_lx/cache_as_ram.inc</span><br><span>index 8250d72..1569cc3 100644</span><br><span>--- a/src/cpu/amd/geode_lx/cache_as_ram.inc</span><br><span>+++ b/src/cpu/amd/geode_lx/cache_as_ram.inc</span><br><span>@@ -183,25 +183,11 @@</span><br><span> /* Call romstage.c main function */</span><br><span> call mainboard_romstage_entry</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-.global done_cache_as_ram_main</span><br><span style="color: hsl(0, 100%, 40%);">-done_cache_as_ram_main:</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Switch from Cache as RAM to real RAM. */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Invalidate the cache since there is nothing on the stack */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Then re-enable the cache */</span><br><span style="color: hsl(120, 100%, 40%);">+ invd</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* We now run over the stack-in-cache,</span><br><span style="color: hsl(0, 100%, 40%);">- * copying it back to itself to invalidate the cache */</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- push %edi</span><br><span style="color: hsl(0, 100%, 40%);">- mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx</span><br><span style="color: hsl(0, 100%, 40%);">- push %esi</span><br><span style="color: hsl(0, 100%, 40%);">- mov $(CONFIG_DCACHE_RAM_BASE),%edi</span><br><span style="color: hsl(0, 100%, 40%);">- mov %edi,%esi</span><br><span style="color: hsl(0, 100%, 40%);">- cld</span><br><span style="color: hsl(0, 100%, 40%);">- rep movsl %ds:(%esi),%es:(%edi)</span><br><span style="color: hsl(0, 100%, 40%);">- pop %esi</span><br><span style="color: hsl(0, 100%, 40%);">- pop %edi</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* Clear the cache out to RAM */</span><br><span style="color: hsl(0, 100%, 40%);">- wbinvd</span><br><span style="color: hsl(0, 100%, 40%);">- /* re-enable the cache */</span><br><span> movl %cr0, %eax</span><br><span> xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */</span><br><span> movl %eax, %cr0</span><br><span>diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>index 8fe2dc0..e59873f 100644</span><br><span>--- a/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/alix1c/romstage.c</span><br><span>@@ -115,35 +115,5 @@</span><br><span> </span><br><span> sdram_initialize(1, memctrl);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Switch from Cache as RAM to real RAM.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * There are two ways we could think about this.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 1. If we are using the romstage.inc ROMCC way, the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * going to be re-setup in the code following this code. Just</span><br><span style="color: hsl(0, 100%, 40%);">- * wbinvd the stack to clear the cache tags. We don't care</span><br><span style="color: hsl(0, 100%, 40%);">- * where the stack used to be.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 2. This file is built as a normal .c -> .o and linked in</span><br><span style="color: hsl(0, 100%, 40%);">- * etc. The stack might be used to return etc. That means we</span><br><span style="color: hsl(0, 100%, 40%);">- * care about what is in the stack. If we are smart we set</span><br><span style="color: hsl(0, 100%, 40%);">- * the CAR stack to the same location as the rest of</span><br><span style="color: hsl(0, 100%, 40%);">- * coreboot. If that is the case we can just do a wbinvd.</span><br><span style="color: hsl(0, 100%, 40%);">- * The stack will be written into real RAM that is now setup</span><br><span style="color: hsl(0, 100%, 40%);">- * and we continue like nothing happened. If the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * located somewhere other than where LB would like it, you</span><br><span style="color: hsl(0, 100%, 40%);">- * need to write some code to do a copy from cache to RAM</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * We use method 1 on Norwich and on this board too.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span> post_code(0x02);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "POST 02\n");</span><br><span style="color: hsl(0, 100%, 40%);">- __asm__("wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Past wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We are finding the return does not work on this board. Explicitly</span><br><span style="color: hsl(0, 100%, 40%);">- * call the label that is after the call to us. This is gross, but</span><br><span style="color: hsl(0, 100%, 40%);">- * sometimes at this level it is the only way out.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- done_cache_as_ram_main();</span><br><span> }</span><br><span>diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>index da3913d..b05140c 100644</span><br><span>--- a/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/alix2d/romstage.c</span><br><span>@@ -138,35 +138,5 @@</span><br><span> </span><br><span> sdram_initialize(1, memctrl);</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- /* Switch from Cache as RAM to real RAM.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * There are two ways we could think about this.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 1. If we are using the romstage.inc ROMCC way, the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * going to be re-setup in the code following this code. Just</span><br><span style="color: hsl(0, 100%, 40%);">- * wbinvd the stack to clear the cache tags. We don't care</span><br><span style="color: hsl(0, 100%, 40%);">- * where the stack used to be.</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * 2. This file is built as a normal .c -> .o and linked in</span><br><span style="color: hsl(0, 100%, 40%);">- * etc. The stack might be used to return etc. That means we</span><br><span style="color: hsl(0, 100%, 40%);">- * care about what is in the stack. If we are smart we set</span><br><span style="color: hsl(0, 100%, 40%);">- * the CAR stack to the same location as the rest of</span><br><span style="color: hsl(0, 100%, 40%);">- * coreboot. If that is the case we can just do a wbinvd.</span><br><span style="color: hsl(0, 100%, 40%);">- * The stack will be written into real RAM that is now setup</span><br><span style="color: hsl(0, 100%, 40%);">- * and we continue like nothing happened. If the stack is</span><br><span style="color: hsl(0, 100%, 40%);">- * located somewhere other than where LB would like it, you</span><br><span style="color: hsl(0, 100%, 40%);">- * need to write some code to do a copy from cache to RAM</span><br><span style="color: hsl(0, 100%, 40%);">- *</span><br><span style="color: hsl(0, 100%, 40%);">- * We use method 1 on Norwich and on this board too.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span> post_code(0x02);</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "POST 02\n");</span><br><span style="color: hsl(0, 100%, 40%);">- __asm__("wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">- printk(BIOS_ERR, "Past wbinvd\n");</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- /* We are finding the return does not work on this board. Explicitly</span><br><span style="color: hsl(0, 100%, 40%);">- * call the label that is after the call to us. This is gross, but</span><br><span style="color: hsl(0, 100%, 40%);">- * sometimes at this level it is the only way out.</span><br><span style="color: hsl(0, 100%, 40%);">- */</span><br><span style="color: hsl(0, 100%, 40%);">- done_cache_as_ram_main();</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27749">change 27749</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/27749"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I21f2341091d49d105026a12022c52d811d71feeb </div>
<div style="display:none"> Gerrit-Change-Number: 27749 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>