[coreboot-gerrit] Change in coreboot[master]: mb/pcengines/apu2: correct GPIO and LED setting
Michał Żygowski (Code Review)
gerrit at coreboot.org
Fri Jul 27 16:17:24 CEST 2018
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/27665
Change subject: mb/pcengines/apu2: correct GPIO and LED setting
......................................................................
mb/pcengines/apu2: correct GPIO and LED setting
Due to vendor's requirements LED 2 and LED3 should be turned
off in late boot process. Add appropriate functions to read
status. Change GPIO setting to use IOMUX to refer to GPIO by
IOMUX register as in BKDG.
Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196
Signed-off-by: Michał Żygowski <michal.zygowski at 3mdeb.com>
---
M src/mainboard/pcengines/apu2/gpio_ftns.c
M src/mainboard/pcengines/apu2/gpio_ftns.h
M src/mainboard/pcengines/apu2/mainboard.c
M src/mainboard/pcengines/apu2/romstage.c
4 files changed, 70 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27665/1
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c
index 12b8f94..c55bafb 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.c
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c
@@ -19,19 +19,37 @@
#include "FchPlatform.h"
#include "gpio_ftns.h"
-void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
+void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)
{
- u8 bdata;
- u8 *memptr;
+ u32 bdata;
+ u32 *memptr;
+ u8 *iomuxptr;
- memptr = (u8 *)(base_addr + IOMUX_OFFSET + iomux_gpio);
- *memptr = iomux_ftn;
-
- memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);
+ memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio);
bdata = *memptr;
- bdata &= 0x07;
- bdata |= setting; /* set direction and data value */
+
+ /* out the data value to prevent glitches */
+ bdata |= (setting & GPIO_OUTPUT_ENABLE);
*memptr = bdata;
+
+ /* set direction and data value */
+ bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE | GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE));
+ *memptr = bdata;
+
+ iomuxptr = (u8 *)(ACPI_MMIO_BASE + IOMUX_OFFSET + iomux_gpio);
+ *iomuxptr = iomux_ftn & 0x3;
+}
+
+u8 read_gpio(u32 gpio)
+{
+ u32 *memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio);
+ return (*memptr & GPIO_PIN_STS) ? 1 : 0;
+}
+
+void write_gpio(u32 gpio, u8 value)
+{
+ u32 *memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio);
+ *memptr |= (value > 0) ? GPIO_OUTPUT_VALUE : 0;
}
int get_spd_offset(void)
diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h
index e08ee7b..24d6a7f 100644
--- a/src/mainboard/pcengines/apu2/gpio_ftns.h
+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h
@@ -16,7 +16,9 @@
#ifndef GPIO_FTNS_H
#define GPIO_FTNS_H
-void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);
+u8 read_gpio(u32 gpio);
+void write_gpio(u32 gpio, u8 value);
int get_spd_offset(void);
#define IOMUX_OFFSET 0xD00
@@ -27,6 +29,7 @@
// http://www.pcengines.ch/schema/apu2c.pdf
// http://www.pcengines.ch/schema/apu3a.pdf
//
+#define IOMUX_GPIO_22 0x09 // MODESW (APU5)
#define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5)
#define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5)
#define IOMUX_GPIO_49 0x40 // STRAP0
@@ -41,6 +44,7 @@
#define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5)
#define IOMUX_GPIO_71 0x4D // PROCHOT
+#define GPIO_22 0x24 // MODESW (APU5)
#define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5)
#define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5)
#define GPIO_49 0x100 // STRAP0
@@ -55,9 +59,10 @@
#define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5)
#define GPIO_71 0x134 // PROCHOT
-#define GPIO_OUTPUT_ENABLE 23
-#define GPIO_OUTPUT_VALUE 22
-#define GPIO_PULL_DOWN_ENABLE 21
-#define GPIO_PULL_UP_ENABLE 20
+#define GPIO_OUTPUT_ENABLE BIT23
+#define GPIO_OUTPUT_VALUE BIT22
+#define GPIO_PULL_DOWN_ENABLE BIT21
+#define GPIO_PULL_UP_ENABLE BIT20
+#define GPIO_PIN_STS BIT16
#endif /* GPIO_FTNS_H */
diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c
index 8f2d622..b93eb72 100644
--- a/src/mainboard/pcengines/apu2/mainboard.c
+++ b/src/mainboard/pcengines/apu2/mainboard.c
@@ -178,6 +178,15 @@
pirq_setup();
}
+static void mainboard_final(void *chip_info)
+{
+ //
+ // Turn off LED 2 and 3
+ //
+ write_gpio(GPIO_58, 1);
+ write_gpio(GPIO_59, 1);
+}
+
/*
* We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address
* into the smbios serial number location.
@@ -228,4 +237,5 @@
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
+ .final = mainboard_final,
};
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index e35afc0..fec25b4 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -113,42 +113,45 @@
//
// Configure output disabled, value low, pull up/down disabled
//
+ if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
+ configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting);
+ }
+
if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) ||
IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
- configure_gpio(ACPI_MMIO_BASE,
- IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
}
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
+ configure_gpio(IOMUX_GPIO_49, Function2, GPIO_49, setting);
+ configure_gpio(IOMUX_GPIO_50, Function2, GPIO_50, setting);
+ configure_gpio(IOMUX_GPIO_71, Function0, GPIO_71, setting);
+
//
// Configure output enabled, value low, pull up/down disabled
//
- setting = 0x1 << GPIO_OUTPUT_ENABLE;
+ setting = GPIO_OUTPUT_ENABLE;
if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||
IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {
- configure_gpio(ACPI_MMIO_BASE,
- IOMUX_GPIO_33, Function0, GPIO_33, setting);
+ configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
+ configure_gpio(IOMUX_GPIO_57, Function1, GPIO_57, setting);
+ configure_gpio(IOMUX_GPIO_58, Function1, GPIO_58, setting);
+ configure_gpio(IOMUX_GPIO_59, Function3, GPIO_59, setting);
+
//
// Configure output enabled, value high, pull up/down disabled
//
- setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
+ setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;
+
if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {
- configure_gpio(ACPI_MMIO_BASE,
- IOMUX_GPIO_32, Function0, GPIO_32, setting);
- configure_gpio(ACPI_MMIO_BASE,
- IOMUX_GPIO_33, Function0, GPIO_33, setting);
+ configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);
}
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
+ configure_gpio(IOMUX_GPIO_51, Function2, GPIO_51, setting);
+ configure_gpio(IOMUX_GPIO_55, Function3, GPIO_55, setting);
+ configure_gpio(IOMUX_GPIO_64, Function2, GPIO_64, setting);
+ configure_gpio(IOMUX_GPIO_68, Function0, GPIO_68, setting);
}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196
Gerrit-Change-Number: 27665
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski at 3mdeb.com>
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