<p>Michał Żygowski has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27665">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/pcengines/apu2: correct GPIO and LED setting<br><br>Due to vendor's requirements LED 2 and LED3 should be turned<br>off in late boot process. Add appropriate functions to read<br>status. Change GPIO setting to use IOMUX to refer to GPIO by<br>IOMUX register as in BKDG.<br><br>Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196<br>Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com><br>---<br>M src/mainboard/pcengines/apu2/gpio_ftns.c<br>M src/mainboard/pcengines/apu2/gpio_ftns.h<br>M src/mainboard/pcengines/apu2/mainboard.c<br>M src/mainboard/pcengines/apu2/romstage.c<br>4 files changed, 70 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/27665/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c</span><br><span>index 12b8f94..c55bafb 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/gpio_ftns.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/gpio_ftns.c</span><br><span>@@ -19,19 +19,37 @@</span><br><span> #include "FchPlatform.h"</span><br><span> #include "gpio_ftns.h"</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)</span><br><span style="color: hsl(120, 100%, 40%);">+void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting)</span><br><span> {</span><br><span style="color: hsl(0, 100%, 40%);">- u8 bdata;</span><br><span style="color: hsl(0, 100%, 40%);">- u8 *memptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 bdata;</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *memptr;</span><br><span style="color: hsl(120, 100%, 40%);">+ u8 *iomuxptr;</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- memptr = (u8 *)(base_addr + IOMUX_OFFSET + iomux_gpio);</span><br><span style="color: hsl(0, 100%, 40%);">- *memptr = iomux_ftn;</span><br><span style="color: hsl(0, 100%, 40%);">-</span><br><span style="color: hsl(0, 100%, 40%);">- memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+ memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio);</span><br><span> bdata = *memptr;</span><br><span style="color: hsl(0, 100%, 40%);">- bdata &= 0x07;</span><br><span style="color: hsl(0, 100%, 40%);">- bdata |= setting; /* set direction and data value */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* out the data value to prevent glitches */</span><br><span style="color: hsl(120, 100%, 40%);">+ bdata |= (setting & GPIO_OUTPUT_ENABLE);</span><br><span> *memptr = bdata;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ /* set direction and data value */</span><br><span style="color: hsl(120, 100%, 40%);">+ bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE | GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE));</span><br><span style="color: hsl(120, 100%, 40%);">+ *memptr = bdata;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ iomuxptr = (u8 *)(ACPI_MMIO_BASE + IOMUX_OFFSET + iomux_gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+ *iomuxptr = iomux_ftn & 0x3;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+u8 read_gpio(u32 gpio)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+ return (*memptr & GPIO_PIN_STS) ? 1 : 0;</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void write_gpio(u32 gpio, u8 value)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ u32 *memptr = (u32 *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+ *memptr |= (value > 0) ? GPIO_OUTPUT_VALUE : 0;</span><br><span> }</span><br><span> </span><br><span> int get_spd_offset(void)</span><br><span>diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h</span><br><span>index e08ee7b..24d6a7f 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/gpio_ftns.h</span><br><span>+++ b/src/mainboard/pcengines/apu2/gpio_ftns.h</span><br><span>@@ -16,7 +16,9 @@</span><br><span> #ifndef GPIO_FTNS_H</span><br><span> #define GPIO_FTNS_H</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-void configure_gpio(uintptr_t base_addr, u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);</span><br><span style="color: hsl(120, 100%, 40%);">+void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting);</span><br><span style="color: hsl(120, 100%, 40%);">+u8 read_gpio(u32 gpio);</span><br><span style="color: hsl(120, 100%, 40%);">+void write_gpio(u32 gpio, u8 value);</span><br><span> int get_spd_offset(void);</span><br><span> </span><br><span> #define IOMUX_OFFSET 0xD00</span><br><span>@@ -27,6 +29,7 @@</span><br><span> // http://www.pcengines.ch/schema/apu2c.pdf</span><br><span> // http://www.pcengines.ch/schema/apu3a.pdf</span><br><span> //</span><br><span style="color: hsl(120, 100%, 40%);">+#define IOMUX_GPIO_22 0x09 // MODESW (APU5)</span><br><span> #define IOMUX_GPIO_32 0x59 // MODESW (SIMSWAP2 on APU5)</span><br><span> #define IOMUX_GPIO_33 0x5A // SIMSWAP (SIMSWAP3 on APU5)</span><br><span> #define IOMUX_GPIO_49 0x40 // STRAP0</span><br><span>@@ -41,6 +44,7 @@</span><br><span> #define IOMUX_GPIO_68 0x48 // PE4_WDIS (SIMSWAP1 on APU5)</span><br><span> #define IOMUX_GPIO_71 0x4D // PROCHOT</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_22 0x24 // MODESW (APU5)</span><br><span> #define GPIO_32 0x164 // MODESW (SIMSWAP2 on APU5)</span><br><span> #define GPIO_33 0x168 // SIMSWAP (SIMSWAP3 on APU5)</span><br><span> #define GPIO_49 0x100 // STRAP0</span><br><span>@@ -55,9 +59,10 @@</span><br><span> #define GPIO_68 0x120 // PE4_WDIS (SIMSWAP1 on APU5)</span><br><span> #define GPIO_71 0x134 // PROCHOT</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_OUTPUT_ENABLE 23</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_OUTPUT_VALUE 22</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_PULL_DOWN_ENABLE 21</span><br><span style="color: hsl(0, 100%, 40%);">-#define GPIO_PULL_UP_ENABLE 20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_OUTPUT_ENABLE BIT23</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_OUTPUT_VALUE BIT22</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PULL_DOWN_ENABLE BIT21</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PULL_UP_ENABLE BIT20</span><br><span style="color: hsl(120, 100%, 40%);">+#define GPIO_PIN_STS BIT16</span><br><span> </span><br><span> #endif /* GPIO_FTNS_H */</span><br><span>diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c</span><br><span>index 8f2d622..b93eb72 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/mainboard.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/mainboard.c</span><br><span>@@ -178,6 +178,15 @@</span><br><span> pirq_setup();</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static void mainboard_final(void *chip_info)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ //</span><br><span style="color: hsl(120, 100%, 40%);">+ // Turn off LED 2 and 3</span><br><span style="color: hsl(120, 100%, 40%);">+ //</span><br><span style="color: hsl(120, 100%, 40%);">+ write_gpio(GPIO_58, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+ write_gpio(GPIO_59, 1);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> /*</span><br><span> * We will stuff a modified version of the first NICs (BDF 1:0.0) MAC address</span><br><span> * into the smbios serial number location.</span><br><span>@@ -228,4 +237,5 @@</span><br><span> </span><br><span> struct chip_operations mainboard_ops = {</span><br><span> .enable_dev = mainboard_enable,</span><br><span style="color: hsl(120, 100%, 40%);">+ .final = mainboard_final,</span><br><span> };</span><br><span>diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>index e35afc0..fec25b4 100644</span><br><span>--- a/src/mainboard/pcengines/apu2/romstage.c</span><br><span>+++ b/src/mainboard/pcengines/apu2/romstage.c</span><br><span>@@ -113,42 +113,45 @@</span><br><span> //</span><br><span> // Configure output disabled, value low, pull up/down disabled</span><br><span> //</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_22, Function0, GPIO_22, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU2) ||</span><br><span> IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||</span><br><span> IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE,</span><br><span style="color: hsl(0, 100%, 40%);">- IOMUX_GPIO_32, Function0, GPIO_32, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_49, Function2, GPIO_49, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_50, Function2, GPIO_50, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_71, Function0, GPIO_71, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> //</span><br><span> // Configure output enabled, value low, pull up/down disabled</span><br><span> //</span><br><span style="color: hsl(0, 100%, 40%);">- setting = 0x1 << GPIO_OUTPUT_ENABLE;</span><br><span style="color: hsl(120, 100%, 40%);">+ setting = GPIO_OUTPUT_ENABLE;</span><br><span> if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU3) ||</span><br><span> IS_ENABLED(CONFIG_BOARD_PCENGINES_APU4)) {</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE,</span><br><span style="color: hsl(0, 100%, 40%);">- IOMUX_GPIO_33, Function0, GPIO_33, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_57, Function1, GPIO_57, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_58, Function1, GPIO_58, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_59, Function3, GPIO_59, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> //</span><br><span> // Configure output enabled, value high, pull up/down disabled</span><br><span> //</span><br><span style="color: hsl(0, 100%, 40%);">- setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;</span><br><span style="color: hsl(120, 100%, 40%);">+ setting = GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (IS_ENABLED(CONFIG_BOARD_PCENGINES_APU5)) {</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE,</span><br><span style="color: hsl(0, 100%, 40%);">- IOMUX_GPIO_32, Function0, GPIO_32, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE,</span><br><span style="color: hsl(0, 100%, 40%);">- IOMUX_GPIO_33, Function0, GPIO_33, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_32, Function0, GPIO_32, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_33, Function0, GPIO_33, setting);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);</span><br><span style="color: hsl(0, 100%, 40%);">- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_51, Function2, GPIO_51, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_55, Function3, GPIO_55, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_64, Function2, GPIO_64, setting);</span><br><span style="color: hsl(120, 100%, 40%);">+ configure_gpio(IOMUX_GPIO_68, Function0, GPIO_68, setting);</span><br><span> }</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27665">change 27665</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Icf4a60acabe65cd7f9985bb3af8bd577764d4196 </div>
<div style="display:none"> Gerrit-Change-Number: 27665 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Michał Żygowski <michal.zygowski@3mdeb.com> </div>