[coreboot-gerrit] Change in coreboot[master]: cpu/intel/model_1067x: Configure IA32_FEATURE_CONTROL for SMRR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/27586


Change subject: cpu/intel/model_1067x: Configure IA32_FEATURE_CONTROL for SMRR
......................................................................

cpu/intel/model_1067x: Configure IA32_FEATURE_CONTROL for SMRR

The SMRR enable bit and lock bit in IA32_FEATURE_CONTROL need to be set before
writing to MSR_SMRR_PHYSBASE and MSR_SMRR_PHYSMASK of model_1067x and model_6fx.
Therefore configureing IA32_FEATURE_CONTROL needs to be done early on these
CPUs.

This change takes away the possibility to not lock VMX on these CPU's as this is
need for SMRR MSR to work.

Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/common/common_init.c
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_1067x/mp_init.c
M src/cpu/intel/model_6fx/Kconfig
M src/cpu/intel/model_6fx/model_6fx_init.c
6 files changed, 27 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/27586/1

diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 44a316b..1e94d4e 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -59,6 +59,18 @@
 			msr.lo |= (1 << 1);
 	}
 
+	/* set SMRR enable bit */
+	if (IS_ENABLED(CONFIG_PARALLEL_MP)) {
+		struct cpuinfo_x86 c;
+
+		get_fms(&c, cpuid_eax(1));
+		if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) {
+			printk(BIOS_DEBUG, "Enabling SMRR\n");
+			/* MSRR enable */
+			msr.lo |= (1 << 3);
+		}
+	}
+
 	wrmsr(IA32_FEATURE_CONTROL, msr);
 
 	if (lock) {
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 3ea8125..1110394 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -10,3 +10,4 @@
 	select TSC_SYNC_MFENCE
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
+	select SET_VMX_LOCK_BIT if SMM_TSEG
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index a2962ae..cb7ba6f 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -300,7 +300,11 @@
 	/* Initialize the APIC timer */
 	init_timer();
 
-	set_vmx();
+	/* Set virtualization based on Kconfig option */
+	/* On parallel MP init we do this earlier since we need to
+	   set bit3 and bit0 on IA32_FEATURE_CONTROL for SMRR to work */
+	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+		set_vmx();
 
 	/* Configure C States */
 	configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index 871a153..5f1c6cb 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -53,6 +53,10 @@
 
 static void per_cpu_smm_trigger(void)
 {
+	/* On model_6fx and model_1067x we need to set the SMRR enable and
+	   lock bit early, so set up configuring IA32_FEATURE_CONTROL early
+	   on. */
+	set_vmx();
 	/* Relocate the SMM handler. */
 	smm_relocate();
 
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index 8f05314..b9d2beb 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -11,3 +11,4 @@
 	select TSC_SYNC_MFENCE
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
+	select SET_VMX_LOCK_BIT if SMM_TSEG
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index eeea9e3..4937693 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -154,7 +154,10 @@
 	setup_lapic();
 
 	/* Set virtualization based on Kconfig option */
-	set_vmx();
+	/* On parallel MP init we do this earlier since we need to
+	   set bit3 and bit0 on IA32_FEATURE_CONTROL for SMRR to work */
+	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+		set_vmx();
 
 	/* Configure C States */
 	configure_c_states();

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b
Gerrit-Change-Number: 27586
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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