<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/27586">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/model_1067x: Configure IA32_FEATURE_CONTROL for SMRR<br><br>The SMRR enable bit and lock bit in IA32_FEATURE_CONTROL need to be set before<br>writing to MSR_SMRR_PHYSBASE and MSR_SMRR_PHYSMASK of model_1067x and model_6fx.<br>Therefore configureing IA32_FEATURE_CONTROL needs to be done early on these<br>CPUs.<br><br>This change takes away the possibility to not lock VMX on these CPU's as this is<br>need for SMRR MSR to work.<br><br>Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/cpu/intel/common/common_init.c<br>M src/cpu/intel/model_1067x/Kconfig<br>M src/cpu/intel/model_1067x/model_1067x_init.c<br>M src/cpu/intel/model_1067x/mp_init.c<br>M src/cpu/intel/model_6fx/Kconfig<br>M src/cpu/intel/model_6fx/model_6fx_init.c<br>6 files changed, 27 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/27586/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c</span><br><span>index 44a316b..1e94d4e 100644</span><br><span>--- a/src/cpu/intel/common/common_init.c</span><br><span>+++ b/src/cpu/intel/common/common_init.c</span><br><span>@@ -59,6 +59,18 @@</span><br><span> msr.lo |= (1 << 1);</span><br><span> }</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ /* set SMRR enable bit */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (IS_ENABLED(CONFIG_PARALLEL_MP)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ struct cpuinfo_x86 c;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ get_fms(&c, cpuid_eax(1));</span><br><span style="color: hsl(120, 100%, 40%);">+ if (c.x86 == 6 && (c.x86_model == 0xf || c.x86_model == 0x17)) {</span><br><span style="color: hsl(120, 100%, 40%);">+ printk(BIOS_DEBUG, "Enabling SMRR\n");</span><br><span style="color: hsl(120, 100%, 40%);">+ /* MSRR enable */</span><br><span style="color: hsl(120, 100%, 40%);">+ msr.lo |= (1 << 3);</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> wrmsr(IA32_FEATURE_CONTROL, msr);</span><br><span> </span><br><span> if (lock) {</span><br><span>diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig</span><br><span>index 3ea8125..1110394 100644</span><br><span>--- a/src/cpu/intel/model_1067x/Kconfig</span><br><span>+++ b/src/cpu/intel/model_1067x/Kconfig</span><br><span>@@ -10,3 +10,4 @@</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span> select CPU_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+ select SET_VMX_LOCK_BIT if SMM_TSEG</span><br><span>diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>index a2962ae..cb7ba6f 100644</span><br><span>--- a/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>+++ b/src/cpu/intel/model_1067x/model_1067x_init.c</span><br><span>@@ -300,7 +300,11 @@</span><br><span> /* Initialize the APIC timer */</span><br><span> init_timer();</span><br><span> </span><br><span style="color: hsl(0, 100%, 40%);">- set_vmx();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Set virtualization based on Kconfig option */</span><br><span style="color: hsl(120, 100%, 40%);">+ /* On parallel MP init we do this earlier since we need to</span><br><span style="color: hsl(120, 100%, 40%);">+ set bit3 and bit0 on IA32_FEATURE_CONTROL for SMRR to work */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))</span><br><span style="color: hsl(120, 100%, 40%);">+ set_vmx();</span><br><span> </span><br><span> /* Configure C States */</span><br><span> configure_c_states(quad);</span><br><span>diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c</span><br><span>index 871a153..5f1c6cb 100644</span><br><span>--- a/src/cpu/intel/model_1067x/mp_init.c</span><br><span>+++ b/src/cpu/intel/model_1067x/mp_init.c</span><br><span>@@ -53,6 +53,10 @@</span><br><span> </span><br><span> static void per_cpu_smm_trigger(void)</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* On model_6fx and model_1067x we need to set the SMRR enable and</span><br><span style="color: hsl(120, 100%, 40%);">+ lock bit early, so set up configuring IA32_FEATURE_CONTROL early</span><br><span style="color: hsl(120, 100%, 40%);">+ on. */</span><br><span style="color: hsl(120, 100%, 40%);">+ set_vmx();</span><br><span> /* Relocate the SMM handler. */</span><br><span> smm_relocate();</span><br><span> </span><br><span>diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig</span><br><span>index 8f05314..b9d2beb 100644</span><br><span>--- a/src/cpu/intel/model_6fx/Kconfig</span><br><span>+++ b/src/cpu/intel/model_6fx/Kconfig</span><br><span>@@ -11,3 +11,4 @@</span><br><span> select TSC_SYNC_MFENCE</span><br><span> select SUPPORT_CPU_UCODE_IN_CBFS</span><br><span> select CPU_INTEL_COMMON</span><br><span style="color: hsl(120, 100%, 40%);">+ select SET_VMX_LOCK_BIT if SMM_TSEG</span><br><span>diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>index eeea9e3..4937693 100644</span><br><span>--- a/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>+++ b/src/cpu/intel/model_6fx/model_6fx_init.c</span><br><span>@@ -154,7 +154,10 @@</span><br><span> setup_lapic();</span><br><span> </span><br><span> /* Set virtualization based on Kconfig option */</span><br><span style="color: hsl(0, 100%, 40%);">- set_vmx();</span><br><span style="color: hsl(120, 100%, 40%);">+ /* On parallel MP init we do this earlier since we need to</span><br><span style="color: hsl(120, 100%, 40%);">+ set bit3 and bit0 on IA32_FEATURE_CONTROL for SMRR to work */</span><br><span style="color: hsl(120, 100%, 40%);">+ if (!IS_ENABLED(CONFIG_PARALLEL_MP))</span><br><span style="color: hsl(120, 100%, 40%);">+ set_vmx();</span><br><span> </span><br><span> /* Configure C States */</span><br><span> configure_c_states();</span><br><span></span><br></pre><p>To view, visit <a href="https://review.coreboot.org/27586">change 27586</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b </div>
<div style="display:none"> Gerrit-Change-Number: 27586 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>