[coreboot-gerrit] Change in coreboot[master]: riscv: clean up redundancy in Makefile

[Xiang Wang (Code Review)]

Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/27557 )

Change subject: riscv: clean up redundancy in Makefile
......................................................................

riscv: clean up redundancy in Makefile

src/arch/riscv/stages.c is a entry of romstage/ramstage, and does not 
need in bootblock.

Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27557/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Gerrit-Change-Number: 27557
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
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