[coreboot-gerrit] Change in coreboot[master]: riscv: clean up redundancy in Makefile

[Xiang Wang (Code Review)]

Xiang Wang has uploaded this change for review. ( https://review.coreboot.org/27557


Change subject: riscv: clean up redundancy in Makefile
......................................................................

riscv: clean up redundancy in Makefile

src/arch/riscv/stages.c is a entry of romstage/ramstage, and does not need in bootblock.

Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27557/1

diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index e00469b..44a5eae 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -42,7 +42,7 @@
 bootblock-y += id.S
 $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
 
-bootblock-y = bootblock.S stages.c
+bootblock-y = bootblock.S
 bootblock-y += trap_util.S
 bootblock-y += trap_handler.c
 bootblock-y += mcall.c

-- 
To view, visit https://review.coreboot.org/27557
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Gerrit-Change-Number: 27557
Gerrit-PatchSet: 1
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180720/b4cc1192/attachment-0001.html>