[coreboot-gerrit] Change in coreboot[master]: riscv: clean up redundancy in Makefile

[Xiang Wang (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/27557

to look at the new patch set (#3).

Change subject: riscv: clean up redundancy in Makefile
......................................................................

riscv: clean up redundancy in Makefile

src/arch/riscv/stages.c is a entry of romstage/ramstage, and does not 
need in bootblock.

src/arch/riscv/id.S src/arch/riscv/id.ld is used to generate some 
compile/board/time information, which is repeated with src/lib/version.c

Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Makefile.inc
D src/arch/riscv/id.S
D src/arch/riscv/id.ld
3 files changed, 1 insertion(+), 56 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27557/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d
Gerrit-Change-Number: 27557
Gerrit-PatchSet: 3
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
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