[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Update PMC base address for CNP H and LP

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/27523


Change subject: soc/intel/cannonlake: Update PMC base address for CNP H and LP
......................................................................

soc/intel/cannonlake: Update PMC base address for CNP H and LP

PMC base address is different for CNP LP pch and CNP H pch.
Added logic to determine PMC base addrress dynamically based on PCH ID.

BUG=none
BRANCH=none
TEST=none

Change-Id: I833395260e8fb631823bd03192a092df323250fa
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/cannonlake/bootblock/pch.c
M src/soc/intel/cannonlake/include/soc/lpc.h
2 files changed, 45 insertions(+), 5 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/27523/1

diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c
index eb67012..e5bb8e6 100644
--- a/src/soc/intel/cannonlake/bootblock/pch.c
+++ b/src/soc/intel/cannonlake/bootblock/pch.c
@@ -27,12 +27,15 @@
 #include <soc/iomap.h>
 #include <soc/lpc.h>
 #include <soc/p2sb.h>
+#include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 #include <soc/smbus.h>
 
-#define PCR_PSF3_TO_SHDW_PMC_REG_BASE	0x1400
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP	0x1400
+#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 	0x0980
+
 #define PCR_PSFX_TO_SHDW_BAR0	0
 #define PCR_PSFX_TO_SHDW_BAR1	0x4
 #define PCR_PSFX_TO_SHDW_BAR2	0x8
@@ -51,6 +54,37 @@
 #define PCR_DMI_LPCIOD		0x2770
 #define PCR_DMI_LPCIOE		0x2774
 
+static uint8_t get_pch_series(void)
+{
+	uint16_t lpc_did;
+	uint8_t  pch_series;
+
+	lpc_did = (pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID) & 0xFF00);
+
+	if ((lpc_did >> 0x8) == 0x9D)
+		pch_series = PCH_LP;
+	else if ((lpc_did >> 0x08) == 0xA2)
+		pch_series = PCH_H;
+	else
+		pch_series = PCH_UNKNOWN_SERIES;
+
+	return pch_series;
+}
+
+static uint32_t get_pmc_reg_base(void)
+{
+	uint8_t pch_series;
+
+	pch_series = get_pch_series();
+
+	if (pch_series == PCH_H)
+		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H;
+	else if (pch_series == PCH_LP)
+		return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP;
+	else
+		return 0;
+}
+
 static void soc_config_pwrmbase(void)
 {
 	uint32_t reg32;
@@ -91,22 +125,27 @@
 static void soc_config_acpibase(void)
 {
 	uint32_t pmc_reg_value;
+	uint32_t pmc_base_reg;
 
-	pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+	pmc_base_reg = get_pmc_reg_base();
+	if (pmc_base_reg == 0x00)
+		return;
+
+	pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + 
 						PCR_PSFX_TO_SHDW_BAR4);
 
 	if (pmc_reg_value != 0xFFFFFFFF)
 	{
 		/* Disable Io Space before changing the address */
-		pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+		pcr_rmw32(PID_PSF3, pmc_base_reg +
 				PCR_PSFX_T0_SHDW_PCIEN,
 				~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0);
 		/* Program ABASE in PSF3 PMC space BAR4*/
-		pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+		pcr_write32(PID_PSF3, pmc_base_reg +
 				PCR_PSFX_TO_SHDW_BAR4,
 				ACPI_BASE_ADDRESS);
 		/* Enable IO Space */
-		pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE +
+		pcr_rmw32(PID_PSF3, pmc_base_reg +
 				PCR_PSFX_T0_SHDW_PCIEN,
 				~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN);
 	}
diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h
index 3ea9be9..74a731b 100644
--- a/src/soc/intel/cannonlake/include/soc/lpc.h
+++ b/src/soc/intel/cannonlake/include/soc/lpc.h
@@ -17,6 +17,7 @@
 #ifndef _SOC_CANNONLAKE_LPC_H_
 #define _SOC_CANNONLAKE_LPC_H_
 
+#define PCI_DEVICE_ID		0x02
 /* PCI Configuration Space (D31:F0): LPC */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I833395260e8fb631823bd03192a092df323250fa
Gerrit-Change-Number: 27523
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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